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  1. /*
  2. * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
  3. * Copyright (C) 2006-2008 Motorola, Inc.
  4. */
  5.  
  6. /*
  7. * The code contained herein is licensed under the GNU General Public
  8. * License. You may obtain a copy of the GNU General Public License
  9. * Version 2 or later at the following locations:
  10. *
  11. * http://www.opensource.org/licenses/gpl-license.html
  12. * http://www.gnu.org/copyleft/gpl.html
  13. *
  14. * Revision History:
  15. *
  16. * Date Author Comment
  17. * ---------- -------- ------------------------
  18. * 10/06/2006 Motorola Power management support
  19. * 11/10/2006 Motorola Add PLL current drain optimization.
  20. * 12/14/2006 Motorola Change DVFS frequency code.
  21. * 12/25/2006 Motorola Changed local_irq_disable/local_irq_enable to
  22. * local_irq_save/local_irq_restore.
  23. * 01/08/2007 Motorola Implemented MGPER fix for crash after WFI.
  24. * 01/16/2007 Motorola Reset DSM state machine upon wakeup.
  25. * 01/19/2007 Motorola Resolved issue with 133Mhz operating point
  26. * and its divider ratios.
  27. * 02/14/2007 Motorola Add code for DSM statistics gathering.
  28. * 02/26/2007 Motorola Make DSM change dividers in two steps for 133.
  29. * 02/15/2007 Motorola Cache optimization changes
  30. * 04/30/2007 Motorola Wait for end of dithering cycle before
  31. * changing PLL settings.
  32. * 05/12/2007 Motorola Changed comments.
  33. * 06/05/2007 Motorola Changed comments.
  34. * 07/31/2007 Motorola Fix the problem that KernelPanic when inserted USB cable with PC.
  35. * 08/09/2007 Motorola Add comments.
  36. * 25/09/2007 Motorola Change max value of PPM for PLL dithering from 1000 to 2000.
  37. * 11/23/2007 Motorola Add BT LED debug option processing
  38. * 01/08/2008 Motorola Changed some debug information.
  39. */
  40.  
  41.  
  42.  
  43. /*!
  44. * @file mxc_pm.c
  45. *
  46. * @brief This file provides all the kernel level and user level API
  47. * definitions for the CRM_AP, DPLL and DSM modules.
  48. *
  49. * @ingroup LPMD
  50. */
  51.  
  52. /*
  53. * Include Files
  54. */
  55. #include <linux/config.h>
  56. #include <linux/module.h>
  57. #include <linux/interrupt.h>
  58. #include <linux/wait.h>
  59. #include <linux/init.h>
  60. #include <linux/fs.h>
  61. #include <linux/errno.h>
  62. #include <linux/kdev_t.h>
  63. #include <linux/major.h>
  64. #include <linux/mm.h>
  65. #include <linux/devfs_fs_kernel.h>
  66. #include <linux/circ_buf.h>
  67. #include <linux/delay.h>
  68. #ifdef CONFIG_MOT_FEAT_PM_STATS
  69. #include <linux/rtc.h>
  70. #endif
  71. #include <asm/hardware.h>
  72. #include <asm/arch/mxc_pm.h>
  73. #include <asm/arch/clock.h>
  74. #include <asm/arch/spba.h>
  75. #include <asm/io.h>
  76. #include <asm/irq.h>
  77. #include <asm/uaccess.h>
  78. #include <asm/system.h>
  79. #include <asm/mach/time.h>
  80. #include <asm/arch/gpio.h>
  81.  
  82. #include "crm_regs.h"
  83.  
  84. #ifdef CONFIG_MOT_FEAT_PM_STATS
  85. #include <linux/mpm.h>
  86. #endif
  87. #ifdef CONFIG_MOT_FEAT_PM
  88. #include <asm/cacheflush.h>
  89. #include <asm/div64.h>
  90. #include <asm/bootinfo.h>
  91. #endif /* CONFIG_MOT_FEAT_PM */
  92.  
  93. /*!
  94. * Declaring lock to prevent request to change core
  95. * frequency when previous transition is not finished
  96. */
  97. static DEFINE_RAW_SPINLOCK(dvfs_lock);
  98.  
  99. /*
  100. * Test to see if this part is Pass 2 silicon.
  101. */
  102. #ifndef CONFIG_MOT_FEAT_PM
  103. #define MXC91231_PASS_1() (system_rev < CHIP_REV_2_0)
  104. #endif
  105. #define MXC91231_PASS_2_OR_GREATER() (system_rev >= CHIP_REV_2_0)
  106.  
  107. /*
  108. * Voltage Levels
  109. */
  110. #define LO_VOLT 0
  111. #define HI_VOLT 1
  112.  
  113. /*
  114. * MXC_CRMAP_AMCR ACK bypass signals
  115. */
  116. #define AMCR_ACK_BYP 0x007B0000
  117.  
  118. /*
  119. * AVIC Lo Interrupt enable register for low-power modes
  120. */
  121. #define LO_INTR_EN IO_ADDRESS(AVIC_BASE_ADDR + 0x14)
  122.  
  123. /*
  124. * Configuration Options
  125. */
  126. /* Only one of the following options can be chosen */
  127. #undef CONFIG_PLL_NOCLOCK /* This option is broken in HW on MXC91231 P1 & P2 */
  128.  
  129. #ifdef CONFIG_MOT_FEAT_PM
  130. #undef CONFIG_PLL_PATREF /* This option is no longer supported */
  131. #define CONFIG_ALT_PLL
  132. #else
  133. #define CONFIG_PLL_PATREF 1
  134. #undef CONFIG_ALT_PLL /* This option is currently not implemented */
  135. #endif
  136.  
  137.  
  138. /*
  139. * The following options used for DSM
  140. */
  141. #define COUNT32_RESET 1
  142. #define COUNT32_NOT_RESET 0
  143. #define CONFIG_RESET_COUNT32 COUNT32_RESET
  144.  
  145. /* Software Workarounds for Hardware issues on MXC91231 P1 */
  146. /* If SDRAMC issue exists then CRM issue will exist */
  147. #define NO_SDRAMC_RATIO_ISSUE 0
  148. #define CRM_ISSUE 1
  149.  
  150. #ifdef CONFIG_MOT_FEAT_PM
  151. /*
  152. * Address offsets of the CRM_COM registers
  153. */
  154. #define CRM_COM_CSCR_PPD1 0x08000000
  155. #endif /* CONFIG_MOT_FEAT_PM */
  156.  
  157. #ifndef CONFIG_MOT_FEAT_PM
  158. /*
  159. * Address offsets of DPLL registers
  160. */
  161. #define PLL0_DP_CTL (MXC_PLL0_BASE + MXC_PLL_DP_CTL)
  162. #define PLL0_DP_CONFIG (MXC_PLL0_BASE + MXC_PLL_DP_CONFIG)
  163. #define PLL0_DP_OP (MXC_PLL0_BASE + MXC_PLL_DP_OP)
  164. #define PLL0_DP_MFD (MXC_PLL0_BASE + MXC_PLL_DP_MFD)
  165. #define PLL0_DP_MFN (MXC_PLL0_BASE + MXC_PLL_DP_MFN)
  166. #define PLL0_DP_HFSOP (MXC_PLL0_BASE + MXC_PLL_DP_HFS_OP)
  167. #define PLL0_DP_HFSMFD (MXC_PLL0_BASE + MXC_PLL_DP_HFS_MFD)
  168. #define PLL0_DP_HFSMFN (MXC_PLL0_BASE + MXC_PLL_DP_HFS_MFN)
  169. #endif /* CONFIG_MOT_FEAT_PM */
  170.  
  171. #ifdef CONFIG_MOT_FEAT_PM
  172. #define TOG_DIS 0x00020000
  173. #define TOG_EN 0x00010000
  174. #define TOG_SEL 0x80000000
  175. #define TOGC_CNT_VALUE 0x00000A28
  176. #define TOGC_CNT_MASK 0x0000FFFF
  177.  
  178. /*
  179. * De-sense feature: Max value of PPM for PLL dithering
  180. */
  181. #define MAX_PLL_PPM_VALUE 2000
  182.  
  183. /* ESDCTL MDDREN bit description used for automatic SDR / DDR detection */
  184. #define ESDCTL_MISC IO_ADDRESS(ESDCTL_BASE_ADDR + 0x10)
  185. #define ESDCTL_MISC_MDDREN 0x00000004
  186. #define mxc_pm_ddram_detected() \
  187. ((__raw_readl(ESDCTL_MISC) & ESDCTL_MISC_MDDREN) == ESDCTL_MISC_MDDREN)
  188.  
  189. /* Bits used for aggressive clock gating */
  190. #define APRA_ALL_CLK_EN (MXC_CRMAP_APRA_SIMEN | \
  191. MXC_CRMAP_APRA_UART1EN | \
  192. MXC_CRMAP_APRA_UART2EN | \
  193. MXC_CRMAP_APRA_UART3EN | \
  194. MXC_CRMAP_APRA_SAHARA_DIV2_CLK_EN_PASS2)
  195.  
  196. #define APRB_ALL_CLK_EN (MXC_CRMAP_APRB_SDHC1EN | \
  197. MXC_CRMAP_APRB_SDHC2EN)
  198.  
  199. #define ACDER1_ALL_CLK_EN (MXC_CRMAP_ACDER1_CSIEN_PASS2 | \
  200. MXC_CRMAP_ACDER1_SSI1EN | \
  201. MXC_CRMAP_ACDER1_SSI2EN)
  202.  
  203. #define ACDER2_ALL_CLK_EN (MXC_CRMAP_ACDER2_USBEN | \
  204. MXC_CRMAP_ACDER2_NFCEN)
  205.  
  206. #endif /* CONFIG_MOT_FEAT_PM */
  207.  
  208.  
  209. /*
  210. * Bits used for mask
  211. */
  212. #define AP_DELAY_MASK 0x0000ffff
  213. #ifdef CONFIG_MOT_WFN421
  214. #define AP_DELAY_SETTING 0x00030000
  215. #else
  216. #define AP_DELAY_SETTING 0x00090000
  217. #endif /* CONFIG_MOT_WFN421 */
  218. #define ACDR_MASK 0xFFFFF000
  219. #define AVIC_TIMER_INTR_DIS 0xCFFFFFFF
  220. #define AVIC_TIMER_INTR_EN 0x30000000
  221. #define ENABLE_WELL_BIAS 0x1
  222.  
  223. /*
  224. * DPLL0 HFS register values
  225. */
  226. #define DP_HFS_OP 0x000000A0
  227. #define DP_HFS_MFD 0x0000000D
  228. #define DP_HFS_MFN 0x00000003
  229.  
  230. /*
  231. * Timer & Counter values for various DSM registers
  232. */
  233. #define SLEEP_TIME 0x00000002
  234.  
  235. /*
  236. * WARM PERIOD - 150 ckil cycles - approx~= 4ms
  237. */
  238. /* Current drain optimization : crystal WARM period set to 92 ckil cycles - approx~= 2.8ms */
  239. #ifdef CONFIG_MOT_FEAT_PM
  240. #define CALC_WAKE_TIME 0x0000005c
  241. #else
  242. #define CALC_WAKE_TIME 0x00000096
  243. #endif
  244. /*
  245. * LOCK PERIOD - 120 usec needed for PLL relock
  246. */
  247. #define CALC_LOCK_TIME 0x00000004
  248.  
  249. /*
  250. * ARM:AHB:IPG Clock Ratios
  251. */
  252. #ifndef CONFIG_MOT_FEAT_PM
  253.  
  254. #define ARM_AHB_IPG_RATIO_HI 0x00000848
  255. #define ARM_AHB_IPG_RATIO_LO 0x00000836
  256. #define ARM_AHB_IPG_RATIO_266 0x00000824
  257.  
  258. #define ARM_AHB_IPG_CRMRATIO_532 0x00000048
  259. #define ARM_AHB_IPG_CRMRATIO_399 0x00000036
  260. #define ARM_AHB_IPG_CRMRATIO_266 0x00000024
  261.  
  262. #else /* CONFIG_MOT_FEAT_PM */
  263.  
  264. /*
  265. * Note that the following ratio define names are based on the divider
  266. * ratio itself, not on the targeted operating point.
  267. */
  268. #define ARM_AHB_IPG_RATIO_112 0x00000812
  269. #define ARM_AHB_IPG_RATIO_124 0x00000824
  270. #define ARM_AHB_IPG_RATIO_136 0x00000836
  271. #define ARM_AHB_IPG_RATIO_148 0x00000848
  272. #define ARM_AHB_IPG_RATIO_224 0x00000024
  273. #define ARM_AHB_IPG_RATIO_248 0x00000048
  274. #define ARM_AHB_IPG_RATIO_212 0x00000012
  275. #endif /* CONFIG_MOT_FEAT_PM */
  276.  
  277. /*
  278. * Define values used to access the L2 cache controller.
  279. *
  280. * Define the number of wait cycles required by the L2 cache for
  281. * various core frequencies.
  282. */
  283. #ifdef CONFIG_MOT_FEAT_PM
  284.  
  285. #define L2CC_CONTROLREG 0x00000100
  286. #define L2CC_AUXREG 0x00000104
  287.  
  288. #define L2CC_ENABLED 0x01
  289.  
  290. #define L2CC_LATENCY_MASK 0xFFFFFFC0
  291.  
  292. #define L2CC_LATENCY_133 0x00000009
  293. #define L2CC_LATENCY_266 0x00000012
  294. #define L2CC_LATENCY_399 0x0000001B
  295. #define L2CC_LATENCY_532 0x00000024
  296.  
  297. #endif /* CONFIG_MOT_FEAT_PM */
  298.  
  299. /*!
  300. * Enumerations of scaling types - enabling or disabling DFS dividers
  301. */
  302. typedef enum {
  303. DFS_ENABLE = 0,
  304. DFS_DISABLE,
  305. } dvfs_scale_t;
  306.  
  307. #ifdef CONFIG_MOT_FEAT_PM
  308. /*
  309. * Note that dvfs_op_point_t (defined here) must be kept in sync with
  310. * dvfs_op_point_index_t (defined in mxc_pm.h).
  311. */
  312.  
  313. /*!
  314. * Enumerations of operating points
  315. */
  316. typedef enum {
  317. CORE_133 = CORE_FREQ_133,
  318. CORE_266 = CORE_FREQ_266,
  319. CORE_399 = CORE_FREQ_399,
  320. CORE_532 = CORE_FREQ_532,
  321. } dvfs_op_point_t;
  322. #else
  323. /*!
  324. * Enumerations of operating points
  325. */
  326. typedef enum {
  327. CORE_133 = 133,
  328. CORE_266 = 266,
  329. CORE_399 = 399,
  330. CORE_532 = 532,
  331. } dvfs_op_point_t;
  332. #endif
  333.  
  334. #ifdef CONFIG_MOT_FEAT_PM
  335. /*
  336. * cur_dvfs_op_point_index is the current operating point index.
  337. */
  338. static dvfs_op_point_index_t cur_dvfs_op_point_index;
  339. #endif /* CONFIG_MOT_FEAT_PM */
  340.  
  341. /*
  342. * Tree level clock gating
  343. */
  344. static unsigned int gate_stop_wait[NUM_GATE_CTRL] =
  345. { MXC_ACGCR_ACG0_STOP_WAIT, MXC_ACGCR_ACG1_STOP_WAIT,
  346. MXC_ACGCR_ACG3_STOP_WAIT,
  347. MXC_ACGCR_ACG4_STOP_WAIT, MXC_ACGCR_ACG5_STOP_WAIT,
  348. MXC_ACGCR_ACG6_STOP_WAIT
  349. };
  350. static unsigned int gate_stop[NUM_GATE_CTRL] =
  351. { MXC_ACGCR_ACG0_STOP, MXC_ACGCR_ACG1_STOP, MXC_ACGCR_ACG3_STOP,
  352. MXC_ACGCR_ACG4_STOP, MXC_ACGCR_ACG5_STOP, MXC_ACGCR_ACG6_STOP
  353. };
  354. static unsigned int gate_run[NUM_GATE_CTRL] =
  355. { MXC_ACGCR_ACG0_RUN, MXC_ACGCR_ACG1_RUN, MXC_ACGCR_ACG3_RUN,
  356. MXC_ACGCR_ACG4_RUN, MXC_ACGCR_ACG5_RUN, MXC_ACGCR_ACG6_RUN
  357. };
  358.  
  359. #ifdef CONFIG_MOT_FEAT_PM
  360. static unsigned int pll_dp_ctlreg[NUM_PLL] = {PLL0_DP_CTL, PLL1_DP_CTL, PLL2_DP_CTL};
  361. static unsigned int pll_dp_hfs_opreg[NUM_PLL] = {PLL0_DP_HFSOP, PLL1_DP_HFSOP, PLL2_DP_HFSOP};
  362. static unsigned int pll_dp_hfs_mfnreg[NUM_PLL] = {PLL0_DP_HFSMFN, PLL1_DP_HFSMFN, PLL2_DP_HFSMFN};
  363. static unsigned int pll_dp_hfs_mfdreg[NUM_PLL] = {PLL0_DP_HFSMFD, PLL1_DP_HFSMFD, PLL2_DP_HFSMFD};
  364.  
  365. static unsigned int pll_dp_config[NUM_PLL] = {PLL0_DP_CONFIG, PLL1_DP_CONFIG, PLL2_DP_CONFIG};
  366. static unsigned int pll_dp_mfn_minus_reg[NUM_PLL] = {PLL0_DP_MFN_MINUS, PLL1_DP_MFN_MINUS, PLL2_DP_MFN_MINUS};
  367. static unsigned int pll_dp_mfn_plus_reg[NUM_PLL] = {PLL0_DP_MFN_PLUS, PLL1_DP_MFN_PLUS, PLL2_DP_MFN_PLUS};
  368. static unsigned int pll_dp_mfn_togc[NUM_PLL] = {PLL0_DP_MFN_TOGC, PLL1_DP_MFN_TOGC, PLL2_DP_MFN_TOGC};
  369. static unsigned int pll_dp_destat[NUM_PLL] = {PLL0_DP_DESTAT, PLL1_DP_DESTAT, PLL2_DP_DESTAT};
  370.  
  371. static unsigned int l2cc_latency[NUM_DVFSOP_INDEXES] = {
  372. L2CC_LATENCY_133,
  373. L2CC_LATENCY_266,
  374. L2CC_LATENCY_399,
  375. L2CC_LATENCY_532
  376. };
  377.  
  378. /*
  379. * The opinfo structure contains the information required
  380. * to change operating points. This information only applies
  381. * to PLL0 (MCUPLL).
  382. * The structure is initialized with configured values.
  383. * The remaining fields are calculated at run time.
  384. * Refer to the SCMA11 Detailed Technical Specification for additional
  385. * information on the fields that are initialized in this structure.
  386. */
  387. static ap_pll_mfn_values_t opinfo[NUM_DVFSOP_INDEXES] = {
  388. /* 133Mhz */ {
  389. ap_pll_dp_hfs_op: 0x00000050,
  390. ap_pll_dp_hfs_mfn: 0x003B13B1,
  391. ap_pll_dp_hfs_mfd: 0x01FFFFFE,
  392. /*
  393. * We'd like the ratio to be 1:1:2, but the PLL
  394. * output clock must be at least 160Mhz, so we
  395. * choose 2:1:2 instead and set the PLL output
  396. * clock at 266Mhz.
  397. */
  398. divider_ratio: ARM_AHB_IPG_RATIO_212,
  399. },
  400. /* 266Mhz */ {
  401. ap_pll_dp_hfs_op: 0x00000050,
  402. ap_pll_dp_hfs_mfn: 0x003B13B1,
  403. ap_pll_dp_hfs_mfd: 0x01FFFFFE,
  404. divider_ratio: ARM_AHB_IPG_RATIO_124,
  405. },
  406. /* 399Mhz */ {
  407. ap_pll_dp_hfs_op: 0x00000070,
  408. ap_pll_dp_hfs_mfn: 0x01589D89,
  409. ap_pll_dp_hfs_mfd: 0x01FFFFFE,
  410. divider_ratio: ARM_AHB_IPG_RATIO_136,
  411. },
  412. /* 532Mhz */ {
  413. ap_pll_dp_hfs_op: 0x000000A0,
  414. ap_pll_dp_hfs_mfn: 0x00762762,
  415. ap_pll_dp_hfs_mfd: 0x01FFFFFE,
  416. divider_ratio: ARM_AHB_IPG_RATIO_148,
  417. },
  418. };
  419.  
  420. /*
  421. * The ap_usb_pll_mfn_values structure contains information for the
  422. * USBPLL.
  423. */
  424. static ap_pll_mfn_values_t ap_usb_pll_mfn_values = {
  425. ap_pll_dp_hfs_op: 0x00000082,
  426. ap_pll_dp_hfs_mfn: 0x009D89D8,
  427. ap_pll_dp_hfs_mfd: 0x01FFFFFE,
  428. };
  429.  
  430. /* Prototypes */
  431. static int mxc_pm_dither_pll_setup(enum plls pll_number,
  432. ap_pll_mfn_values_t *ap_pll_mfn_values);
  433.  
  434. int mxc_pm_dither_control(int enable, enum plls pll_number);
  435.  
  436. /*
  437. * SEXT does a sign extension on the given value. nbits is the number
  438. * of bits consumed by val, including the sign bit. nbits larger than
  439. * 31 doesn't make sense. This macro just shifts the bits up to the
  440. * top of the word and then back down. This causes the sign bit to
  441. * propagate when shifting back. Note that ANSI C characterizes this
  442. * behavior as implementation defined.
  443. */
  444. #define SEXT(nbits,val) ((((int)(val)) << (32-(nbits))) >> (32-(nbits)))
  445.  
  446. /*
  447. * Convert 27 bits from MFNxxx registers ("false signed values")
  448. * to s32 absolute value. Sign extend the value and then take
  449. * its absolute value.
  450. */
  451. #define DPLL_MFN_TO_ABSOLUTE(val) abs(SEXT(27,val))
  452.  
  453. /*
  454. * Switching to PLL1 when the AP goes to DSM might cause some
  455. * instability, so we're providing a means to disable this behavior
  456. * using pll0_on_in_ap_dsm in the Linux command line. Add
  457. * "pll0_on_in_ap_dsm=on" to the command line to disable the behavior.
  458. * pll0_on_in_ap_dsm is off by default.
  459. *
  460. * asm/setup.h is only needed for the __early_param code.
  461. */
  462. #include <asm/setup.h>
  463. static int pll0_on_in_ap_dsm = 0;
  464.  
  465. static void __init set_pll0_on_in_ap_dsm(char **p)
  466. {
  467. if (memcmp(*p, "on", 2) == 0) {
  468. pll0_on_in_ap_dsm = 1;
  469. *p += 2;
  470. } else if (memcmp(*p, "off", 3) == 0) {
  471. pll0_on_in_ap_dsm = 0;
  472. *p += 3;
  473. }
  474. }
  475.  
  476. __early_param("pll0_on_in_ap_dsm=", set_pll0_on_in_ap_dsm);
  477.  
  478. int pll0_off_in_ap_dsm(void)
  479. {
  480. return (pll0_on_in_ap_dsm == 0);
  481. }
  482.  
  483.  
  484. /*
  485. * mxc_pm_chgfreq_enabled determines when frequency changes are allowed.
  486. */
  487. static int mxc_pm_chgfreq_enabled(dvfs_op_point_t newop, dvfs_op_point_t curop)
  488. {
  489. /*
  490. * No frequency changes of any kind are allowed if the system
  491. * contains DDRAM.
  492. */
  493. if (mxc_pm_ddram_detected())
  494. return 0;
  495.  
  496. return 1;
  497. }
  498. #endif /* CONFIG_MOT_FEAT_PM */
  499.  
  500. /*!
  501. * To check the status of the AP domain core voltage
  502. *
  503. * @return HI_VOLT Returns HI_VOLT indicating that core
  504. * is at Hi voltage (1.6V)
  505. * @return LO_VOLT Returns LO_VOLT indicating that core
  506. * is at Lo voltage (1.2V)
  507. */
  508. static int mxc_pm_chkvoltage(void)
  509. {
  510. /*
  511. * Read the CRM_AP DFS register to get the current
  512. * AP voltage
  513. */
  514. if ((__raw_readl(MXC_CRMAP_ADCR) & MXC_CRMAP_ADCR_VSTAT) != 0) {
  515. return LO_VOLT;
  516. } else {
  517. return HI_VOLT;
  518. }
  519. }
  520.  
  521. #ifndef CONFIG_MOT_FEAT_PM
  522. /*!
  523. * To check the status of the DFS_DIV_EN bit
  524. *
  525. * @return DFS_ENABLE Returns DFS_ENABLE indicating this bit
  526. * is set - implies Integer scaling is
  527. * enabled using DFS dividers
  528. * @return DFS_DISABLE Returns DFS_DISABLE indicating this bit
  529. * is set - implies PLL scaling is used
  530. *
  531. */
  532. static dvfs_scale_t mxc_pm_chkdfs(void)
  533. {
  534. if ((__raw_readl(MXC_CRMAP_ADCR) & MXC_CRMAP_ADCR_DFS_DIVEN) != 0) {
  535. return DFS_ENABLE;
  536. } else {
  537. return DFS_DISABLE;
  538. }
  539. }
  540. #endif /* CONFIG_MOT_FEAT_PM */
  541.  
  542. /*!
  543. * To change the core voltage from Hi to Lo or viceversa
  544. *
  545. * @param val HI_VOLT - Indicating that core requires
  546. * Hi voltage (1.6V)
  547. * LO_VOLT - Indicating that core requires
  548. * Lo voltage (1.2V)
  549. *
  550. */
  551. static void mxc_pm_chgvoltage(int val)
  552. {
  553.  
  554. unsigned long dsm_crm_ctrl;
  555.  
  556. switch (val) {
  557.  
  558. case LO_VOLT:
  559.  
  560. /* Move to Lo Voltage */
  561. if ((__raw_readl(MXC_CRMAP_ADCR) & MXC_CRMAP_ADCR_TSTAT) == 0) {
  562. dsm_crm_ctrl =
  563. __raw_readl(MXC_DSM_CRM_CONTROL) |
  564. (MXC_DSM_CRM_CTRL_DVFS_VCTRL);
  565. __raw_writel(dsm_crm_ctrl, MXC_DSM_CRM_CONTROL);
  566. }
  567. break;
  568.  
  569. case HI_VOLT:
  570.  
  571. /* Setting ap_delay */
  572. __raw_writel(((__raw_readl(MXC_CRMAP_ADCR) & AP_DELAY_MASK) |
  573. AP_DELAY_SETTING), MXC_CRMAP_ADCR);
  574.  
  575. /* Move to Hi Voltage */
  576. dsm_crm_ctrl =
  577. __raw_readl(MXC_DSM_CRM_CONTROL) &
  578. (~MXC_DSM_CRM_CTRL_DVFS_VCTRL);
  579. __raw_writel(dsm_crm_ctrl, MXC_DSM_CRM_CONTROL);
  580.  
  581. /* Wait on the TSTAT timer for voltage to stabilize */
  582. do {
  583. udelay(1);
  584. } while (__raw_readl(MXC_CRMAP_ADCR) & MXC_CRMAP_ADCR_TSTAT);
  585. break;
  586.  
  587. default:
  588. break;
  589. }
  590. }
  591.  
  592. /*!
  593. * To choose one of the scaling techniques either Integer scaling or
  594. * PLL scaling by setting or clearing DFS_DIV_EN bit
  595. *
  596. * @param dfs DFS_ENABLE - Enables Integer scaling -
  597. * to use DFS dividers by setting DFS_DIV_EN bit
  598. *
  599. * DFS_DISABLE - Enables PLL scaling -
  600. * to not use DFS dividers by clearing
  601. * DFS_DIV_EN bit and also setting one of the
  602. * PLL scaling methods,
  603. * PLL using pat_ref or
  604. * PLL using no_clock or - not supported as it is broken in HW
  605. * PLL using ALT_PLL - now supported
  606. *
  607. */
  608. static void mxc_pm_config_scale(dvfs_scale_t dfs)
  609. {
  610. unsigned long adcr;
  611.  
  612. if (dfs == DFS_ENABLE) {
  613. /*
  614. * Set DFS_DIV_EN bit and clear DIV_BYP bit to enable Integer scaling
  615. * Also, clear the ALT_PLL bit
  616. */
  617. adcr =
  618. ((__raw_readl(MXC_CRMAP_ADCR) | MXC_CRMAP_ADCR_DFS_DIVEN) &
  619. ~MXC_CRMAP_ADCR_DIV_BYP) & (~MXC_CRMAP_ADCR_ALT_PLL);
  620. __raw_writel(adcr, MXC_CRMAP_ADCR);
  621. } else if (dfs == DFS_DISABLE) {
  622. /* Disable using DFS divider to enable PLL scaling */
  623.  
  624. #if defined (CONFIG_PLL_PATREF)
  625. /*
  626. * pat_ref clock is used while PLL is relocking. Set CLK_ON bit to
  627. * use pat_ref. Also, set the DIV_BYP bit to bypass DFS divider
  628. * and clear ALT_PLL bit. Clear DFS_DIV_EN bit to select PLL scaling
  629. */
  630. adcr =
  631. (((__raw_readl(MXC_CRMAP_ADCR) | MXC_CRMAP_ADCR_DIV_BYP) |
  632. MXC_CRMAP_ADCR_CLK_ON) & (~MXC_CRMAP_ADCR_ALT_PLL)) &
  633. (~MXC_CRMAP_ADCR_DFS_DIVEN);
  634. __raw_writel(adcr, MXC_CRMAP_ADCR);
  635. #elif defined (CONFIG_PLL_NOCLOCK)
  636. /*
  637. * no clock is used while PLL is relocking. Clear CLK_ON bit to
  638. * not use pat_ref. Also, set the DIV_BYP bit to bypass DFS divider
  639. * and clear ALT_PLL bit. Clear DFS_DIV_EN bit to select PLL scaling
  640. */
  641. adcr =
  642. (((__raw_readl(MXC_CRMAP_ADCR) | MXC_CRMAP_ADCR_DIV_BYP) &
  643. (~MXC_CRMAP_ADCR_CLK_ON)) & (~MXC_CRMAP_ADCR_ALT_PLL))
  644. & (~MXC_CRMAP_ADCR_DFS_DIVEN);
  645. __raw_writel(adcr, MXC_CRMAP_ADCR);
  646. #elif defined (CONFIG_ALT_PLL)
  647. /*
  648. * Clock source from an alternate PLL is used while
  649. * PLL is relocking. Set ALT_PLL bit. Clear DFS_DIV_EN bit
  650. * to select PLL scaling. Set DIV_BYP bit to bypass DFS divider.
  651. * Clear CLK_ON to not use pat_ref
  652. */
  653. adcr = ((__raw_readl(MXC_CRMAP_ADCR) | MXC_CRMAP_ADCR_ALT_PLL) &
  654. (~MXC_CRMAP_ADCR_DFS_DIVEN)) & (~MXC_CRMAP_ADCR_CLK_ON);
  655. __raw_writel(adcr, MXC_CRMAP_ADCR);
  656. #else
  657. #error You must choose one of the Scaling Options
  658. #endif
  659. }
  660. }
  661.  
  662. #ifndef CONFIG_MOT_FEAT_PM
  663. /*!
  664. * Setting possible LFDF value for Integer Scaling
  665. *
  666. * @param value The divider value to be set for the DFS block.
  667. * Possible values are 0,2,4,8.
  668. * This occurs during Integer scaling
  669. *
  670. */
  671. static void mxc_pm_setlfdf(int value)
  672. {
  673. unsigned long adcr_val;
  674.  
  675. adcr_val = (__raw_readl(MXC_CRMAP_ADCR) & (~MXC_CRMAP_ADCR_LFDF_MASK)) |
  676. value;
  677. __raw_writel(adcr_val, MXC_CRMAP_ADCR);
  678. }
  679.  
  680. /*!
  681. * Used on MXC91231 P1 to set MFI, MFN, MFD values in LFS PLL register.
  682. * Using this the output frequency whose value is calculated using,
  683. * 2 * REF_FREQ * (MF / PDF), where
  684. * REF_FREQ is 26 Mhz
  685. * MF = MFI + (MFN / MFD)
  686. * PDF is assumed to be 1
  687. *
  688. * @param armfreq The desired ARM frequency
  689. *
  690. * @return Returns 0 on success or
  691. * Returns -1 on error
  692. */
  693. static void mxc_pm_calc_mf_lfs(long armfreq)
  694. {
  695. signed long dp_opval, mfn, mfd, mfi, ref_freq;
  696. int pdf;
  697.  
  698. ref_freq = mxc_get_clocks(CKIH_CLK) / MEGA_HERTZ;
  699. /*
  700. * Each PLL is identified using base address and
  701. * PLL0 is assumed to be selected for AP domain
  702. * MF is calculated here. PDF is set to 1 which is divide by 2
  703. * by default by hardware
  704. */
  705. pdf = (__raw_readl(PLL0_DP_OP)) & 0xF;
  706. /*
  707. * The following steps calculate the Whole number and fractional
  708. * part of the output frequency using integer arithmetic.
  709. */
  710. mfi = (armfreq * (pdf + 1)) / (2 * ref_freq);
  711. mfn = armfreq - (2 * mfi * ref_freq);
  712. mfd = (2 * ref_freq);
  713. mfi = (mfi <= 5) ? 5 : mfi;
  714. mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
  715. dp_opval = (mfi << 4) | (0x0000000F & __raw_readl(PLL0_DP_OP));
  716. __raw_writel(dp_opval, PLL0_DP_OP);
  717. __raw_writel(mfn, PLL0_DP_MFN);
  718. __raw_writel(mfd, PLL0_DP_MFD);
  719.  
  720. /* Wait until PLL relocks */
  721. while ((__raw_readl(PLL0_DP_CTL) & MXC_PLL_DP_CTL_LRF) !=
  722. MXC_PLL_DP_CTL_LRF) ;
  723. }
  724. #endif /* CONFIG_MOT_FEAT_PM */
  725.  
  726. #ifdef CONFIG_MOT_FEAT_PM
  727. /*
  728. * dvfsop2index converts a dvfs_op_point_t to dvfs_op_point_index_t.
  729. */
  730. static dvfs_op_point_index_t dvfsop2index (dvfs_op_point_t dvfs_op)
  731. {
  732. dvfs_op_point_index_t dvfs_indx = INDX_INVAL;
  733.  
  734. switch (dvfs_op) {
  735. case CORE_133: dvfs_indx = INDX_133; break;
  736. case CORE_266: dvfs_indx = INDX_266; break;
  737. case CORE_399: dvfs_indx = INDX_399; break;
  738. case CORE_532: dvfs_indx = INDX_532; break;
  739. }
  740.  
  741. return dvfs_indx;
  742. }
  743.  
  744. /*
  745. * mxc_pm_set_l2cc_latency is a function that sets the read/write
  746. * latency of the L2 cache controller.
  747. *
  748. * mxc_pm_set_l2cc_latency must be called with interrupts disabled.
  749. *
  750. * dvfs_op_index - requested operating point index.
  751. *
  752. * mxc_pm_set_l2cc_latency returns nothing.
  753. */
  754. static void mxc_pm_set_l2cc_latency (dvfs_op_point_index_t dvfs_op_index)
  755. {
  756. unsigned long control_reg;
  757. unsigned long auxilary_reg;
  758.  
  759. flush_cache_all();
  760. __asm__("mcr p15, 0, r0, c7, c10, 4\n" : : : "r0"); /* Drain the write buffer */
  761.  
  762. control_reg = __raw_readl(L2CC_BASE_ADDR_VIRT+L2CC_CONTROLREG);
  763. control_reg &= ~L2CC_ENABLED;
  764.  
  765. __raw_writel(control_reg, L2CC_BASE_ADDR_VIRT+L2CC_CONTROLREG);
  766.  
  767. __asm__("mcr p15, 0, r0, c7, c10, 4\n" : : : "r0"); /* Drain the write buffer */
  768.  
  769. auxilary_reg = __raw_readl(L2CC_BASE_ADDR_VIRT+L2CC_AUXREG);
  770. auxilary_reg &= L2CC_LATENCY_MASK;
  771. auxilary_reg |= l2cc_latency[dvfs_op_index];
  772.  
  773. __raw_writel(auxilary_reg, L2CC_BASE_ADDR_VIRT+L2CC_AUXREG);
  774.  
  775. __asm__("mcr p15, 0, r0, c7, c10, 4\n" : : : "r0"); /* Drain the write buffer */
  776.  
  777. control_reg = __raw_readl(L2CC_BASE_ADDR_VIRT+L2CC_CONTROLREG);
  778. control_reg |= L2CC_ENABLED;
  779.  
  780. __raw_writel(control_reg, L2CC_BASE_ADDR_VIRT+L2CC_CONTROLREG);
  781. }
  782.  
  783. /* mxc_gpt_udelay is a replace of udelay make use of GPT
  784. *
  785. * usvalue - time want to delay. (us)
  786. *
  787. * Description - LATCH/10ms = ticks_need_to_wait/ (how long we will wait)ms
  788. */
  789. static void mxc_gpt_udelay( unsigned long usvalue )
  790. {
  791. unsigned long now_tick, ticks_to_wait, ticks_delta;
  792.  
  793. now_tick = __raw_readl(MXC_GPT_GPTCNT);
  794. ticks_to_wait = ( usvalue * LATCH * HZ)/1000000;
  795.  
  796. do{
  797. ticks_delta = __raw_readl(MXC_GPT_GPTCNT) - now_tick;
  798. }while ( ticks_delta < ticks_to_wait );
  799.  
  800. }
  801.  
  802. /*
  803. * mxc_pm_chgfreq_common is a common function that does the real work
  804. * of changing frequencies.
  805. *
  806. * mxc_pm_chgfreq_common must be called with interrupts disabled.
  807. *
  808. * dvfs_op_index - dvfs_op_index is the requested
  809. * operating point index.
  810. *
  811. * mxc_pm_chgfreq_common returns nothing.
  812. */
  813. static void mxc_pm_chgfreq_common(dvfs_op_point_index_t dvfs_op_index)
  814. {
  815. unsigned long ascsr;
  816.  
  817. if (dvfs_op_index == cur_dvfs_op_point_index)
  818. return;
  819.  
  820. if ((dvfs_op_index < INDX_FIRST) || (dvfs_op_index >= NUM_DVFSOP_INDEXES))
  821. return;
  822.  
  823. /* Request USBPLL. When this returns, the USBPLL is started and locked. */
  824. mxc_pll_request_pll(USBPLL);
  825.  
  826. /*
  827. * If we are switching to a frequency that requires a longer latency,
  828. * make the switch now so when the frequency change is complete the cache
  829. * still behaves correctly.
  830. */
  831. if(l2cc_latency[cur_dvfs_op_point_index] < l2cc_latency[dvfs_op_index])
  832. mxc_pm_set_l2cc_latency(dvfs_op_index);
  833.  
  834. /*
  835. * ARM:AHB:IPG divider ratio = 1:4:8
  836. *
  837. * We are about to switch to PLL2 (USBPLL). We set the PLL
  838. * dividers to 1:4:8 because it satisfies the requirements
  839. * that SDRAM is <= 133Mhz and the SDRAM:IP frequency is 2:1
  840. * for all PLL0 frequencies that we use (266/399/532) *and*
  841. * the PLL2 frequency (144Mhz). If we were running at 133Mhz,
  842. * we'll slow down the SDRAM and IP clocks pretty well, but
  843. * we're not running on PLL2 for very long, so it's OK.
  844. */
  845. if (cur_dvfs_op_point_index == INDX_133) {
  846. /*
  847. * If we get here, then we are currently operating at
  848. * the 133 operating point.
  849. *
  850. * Note that all operating points except 133 use a
  851. * CPU divider ratio of 1, so the switch can be done
  852. * in one step.
  853. *
  854. * Freescale recommends that returning from a divider
  855. * ratio of 2:1:2 (for operating point 133) should be
  856. * done in two steps. The first step is 2:4:8.
  857. *
  858. * We delay after we write to ensure that the dividers
  859. * are propagated in the correct order. We are
  860. * running now at 2:1:2. We move to 2:4:8 which
  861. * changes only the AHB/IPG dividers. Then we make
  862. * the final change which changes the CPU divider.
  863. *
  864. * Failure to accomplish the divider ratio switch
  865. * in two steps results in system instability.
  866. */
  867. __raw_writel(ARM_AHB_IPG_RATIO_248, MXC_CRMAP_ACDR);
  868. udelay(1);
  869. }
  870. __raw_writel(ARM_AHB_IPG_RATIO_148, MXC_CRMAP_ACDR);
  871.  
  872. /* Switch AP domain to PLL2 (USBPLL) */
  873. ascsr = ((__raw_readl(MXC_CRMAP_ASCSR) & ~ASCSR_APSEL_0) | ASCSR_APSEL_1);
  874. __raw_writel(ascsr, MXC_CRMAP_ASCSR);
  875.  
  876. /*
  877. * If the change in frequency allows us to move to a faster latency, make
  878. * the switch after the change in frequency. This allows the cache up to
  879. * the frequency change to work correctly.
  880. */
  881. if(l2cc_latency[cur_dvfs_op_point_index] > l2cc_latency[dvfs_op_index])
  882. mxc_pm_set_l2cc_latency(dvfs_op_index);
  883.  
  884. mxc_pll_release_pll(MCUPLL);
  885.  
  886. /* Change voltage if necessary. */
  887. if (dvfs_op_index == INDX_532) {
  888. mxc_pm_chgvoltage(HI_VOLT);
  889. } else {
  890. if (mxc_pm_chkvoltage() == HI_VOLT)
  891. mxc_pm_chgvoltage(LO_VOLT);
  892. }
  893. /* Setup dithering of AP Core Normal PLL, if dithering enabled */
  894. if ((__raw_readl(pll_dp_mfn_togc[MCUPLL]) & TOG_DIS) == 0)
  895. {
  896. /* mxc_pm_dither_pll_setup(MCUPLL, &opinfo[dvfs_op_index]); */
  897.  
  898. /* Disable dithering */
  899. mxc_pm_dither_control(0, MCUPLL);
  900.  
  901. /* Disable MCUPLL */
  902. __raw_writel(__raw_readl(pll_dp_ctlreg[MCUPLL]) & ~MXC_PLL_DP_CTL_UPEN, pll_dp_ctlreg[MCUPLL]);
  903.  
  904.  
  905. /* Setup PLL registers */
  906. __raw_writel(opinfo[dvfs_op_index].ap_pll_dp_hfs_mfnminus, pll_dp_mfn_minus_reg[MCUPLL]);
  907. __raw_writel(opinfo[dvfs_op_index].ap_pll_dp_hfs_mfnplus, pll_dp_mfn_plus_reg[MCUPLL]);
  908.  
  909. /* Add a delay longer than a TOG_COUNTER period to make sure dither cycle eventually running is finishe
  910. * Toggle clock reference is CKIH 26 MHz.
  911. * TOG_COUNTER = 0xA28 = 0d2600 for SCM-A11 platform. 2600 * 1 / 26E^10 = 100 us.
  912. * Take in addition a 10 us margin
  913. */
  914. mxc_gpt_udelay(110);
  915.  
  916. /* Generate a load_req */
  917. __raw_writel(__raw_readl(pll_dp_config[MCUPLL]) | DP_LDREQ, pll_dp_config[MCUPLL]);
  918.  
  919. /* Re-enable MCUPLL */
  920. __raw_writel(__raw_readl(pll_dp_ctlreg[MCUPLL]) | MXC_PLL_DP_CTL_UPEN, pll_dp_ctlreg[MCUPLL]);
  921.  
  922. /* Enable dithering, only if ppm value != 0 */
  923. if (opinfo[dvfs_op_index].ap_pll_ppm_value != 0)
  924. mxc_pm_dither_control(1, MCUPLL);
  925.  
  926. }
  927.  
  928.  
  929. /* Load the correct frequency values into the HFS registers. */
  930. __raw_writel(opinfo[dvfs_op_index].ap_pll_dp_hfs_op, pll_dp_hfs_opreg[MCUPLL]);
  931. __raw_writel(opinfo[dvfs_op_index].ap_pll_dp_hfs_mfd, pll_dp_hfs_mfdreg[MCUPLL]);
  932. __raw_writel(opinfo[dvfs_op_index].ap_pll_dp_hfs_mfn, pll_dp_hfs_mfnreg[MCUPLL]);
  933.  
  934.  
  935. /* Request MCUPLL. When this returns, the MCUPLL is started and locked. */
  936. mxc_pll_request_pll(MCUPLL);
  937.  
  938. /* Switch AP domain back on PLL0 */
  939. ascsr = (ascsr & ~MXC_CRMAP_ASCSR_APSEL_MASK);
  940. __raw_writel(ascsr, MXC_CRMAP_ASCSR);
  941.  
  942. mxc_pll_release_pll(USBPLL);
  943.  
  944. if (dvfs_op_index == INDX_133) {
  945. /*
  946. * If we get here, then we are switching to the 133
  947. * operating point.
  948. *
  949. * Freescale recommends that going to a divider ratio
  950. * of 2:1:2 (for operating point 133) should be done
  951. * in two steps. The first step is 2:4:8.
  952. *
  953. * Note that all operating points except 133 use a
  954. * CPU divider ratio of 1, so the switch can be done
  955. * in one step.
  956. *
  957. * We delay after we write to ensure that the dividers
  958. * are propagated in the correct order. We are
  959. * running now at 1:4:8. We move to 2:4:8 which
  960. * changes only the CPU divider. Then we make the
  961. * final change which changes the AHB/IPG dividers.
  962. *
  963. * Failure to accomplish the divider ratio switch
  964. * in two steps results in system instability.
  965. */
  966. __raw_writel(ARM_AHB_IPG_RATIO_248, MXC_CRMAP_ACDR);
  967. udelay(1);
  968. }
  969.  
  970. /* Set the ARM:AHB:IPG divider ratio. */
  971. __raw_writel(opinfo[dvfs_op_index].divider_ratio, MXC_CRMAP_ACDR);
  972.  
  973. cur_dvfs_op_point_index = dvfs_op_index;
  974. }
  975. #endif /* CONFIG_MOT_FEAT_PM */
  976.  
  977. /*!
  978. * To change AP core frequency and/or voltage suitably
  979. *
  980. * @param dvfs_op The values are,
  981. * CORE_133 - ARM desired to run @133MHz, LoV (1.2V)
  982. * CORE_266 - ARM desired to run @266MHz, LoV (1.2V)
  983. * CORE_399 - ARM desired to run @399MHz, LoV (1.2V)
  984. * CORE_532 - ARM desired to run @133MHz, HiV (1.6V)
  985. * The table or sequence os as follows where dividers
  986. * ratio includes, LFDF:ARM:AHB:IPG.
  987. * x ==> LFDF or DFS dividers bypassed
  988. * Pass 1 Pass 2
  989. * PLL Dividers PLL Dividers
  990. * 133 = 266 x:2:2:4 532 4:1:1:2
  991. * 266 = 266 x:1:2:4 532 2:1:2:4
  992. * 399 = 399 x:1:3:6 399 x:1:3:6
  993. * 532 = 532 x:2:2:4 532 x:1:4:8 (on P1, Core is @266Mhz)
  994. *
  995. * @return Returns -ERR_FREQ_INVALID if none of the above choice
  996. * is selected
  997. */
  998. static int mxc_pm_chgfreq(dvfs_op_point_t dvfs_op)
  999. {
  1000. #ifdef CONFIG_MOT_FEAT_PM
  1001. dvfs_op_point_index_t dvfs_op_index;
  1002. #else
  1003. int voltage, dfs_div;
  1004. #endif
  1005.  
  1006. #ifdef CONFIG_MOT_FEAT_PM
  1007. dvfs_op_index = dvfsop2index(dvfs_op);
  1008. if ((dvfs_op_index < INDX_FIRST) || (dvfs_op_index >= NUM_DVFSOP_INDEXES))
  1009. return -ERR_FREQ_INVALID;
  1010.  
  1011. /*
  1012. * If we can't change frequencies, then just return.
  1013. * mxc_pm_chgfreq_enabled() defines when we can change
  1014. * frequencies and when we can't.
  1015. */
  1016. if (!mxc_pm_chgfreq_enabled(dvfs_op_index, cur_dvfs_op_point_index))
  1017. return -MXC_PM_DVFS_DISABLED;
  1018.  
  1019. mxc_pm_chgfreq_common(dvfs_op_index);
  1020.  
  1021. return 0;
  1022.  
  1023. #else /* CONFIG_MOT_FEAT_PM */
  1024.  
  1025. /* Check if AP is in HIGH or in LOW voltage */
  1026. voltage = mxc_pm_chkvoltage();
  1027.  
  1028. /* Check if DFS_DIV is ENABLED or DISABLED */
  1029. dfs_div = mxc_pm_chkdfs();
  1030.  
  1031. switch (dvfs_op) {
  1032.  
  1033. case CORE_133:
  1034. /* INTEGER SCALING */
  1035. if (CRM_ISSUE && MXC91231_PASS_1()) {
  1036. /*
  1037. * Due to HW issue with LFDF dividers, to get 133MHz, PLL is
  1038. * relocked to 266MHz and ARM:AHB:IPG dividers are set to
  1039. * 2:2:4
  1040. */
  1041. mxc_pm_chgfreq(CORE_266);
  1042.  
  1043. /* setting ratio 2:2:4 */
  1044. __raw_writel(((__raw_readl(MXC_CRMAP_ACDR) & ACDR_MASK)
  1045. | ARM_AHB_IPG_CRMRATIO_266),
  1046. MXC_CRMAP_ACDR);
  1047.  
  1048. return 0;
  1049. }
  1050.  
  1051. /*
  1052. * There are two conditions,
  1053. * 1. You have to be at Hi voltage to set DFS dividers
  1054. * 2. If not at Hi voltage, then move to Hi voltage and
  1055. * then set the dividers
  1056. */
  1057. if (voltage == LO_VOLT) {
  1058. /*
  1059. * This implies that we are at 399MHz or 266MHz. So, first change
  1060. * to 532MHz
  1061. */
  1062. /* Raise Voltage */
  1063. mxc_pm_chgfreq(CORE_532);
  1064. }
  1065.  
  1066. /* Configure scaling type to Integer scaling - to use DFS dividers */
  1067. mxc_pm_config_scale(DFS_ENABLE);
  1068.  
  1069. /* Set LFDF to LFDF_4 so that LFDF:ARM:AHB:IPG is 4:1:1:2 */
  1070. mxc_pm_setlfdf(MXC_CRMAP_ADCR_LFDF_4);
  1071.  
  1072. /* Reduce Voltage */
  1073. mxc_pm_chgvoltage(LO_VOLT);
  1074.  
  1075. break;
  1076.  
  1077. case CORE_266:
  1078. /* INTEGER SCALING */
  1079. if (CRM_ISSUE && MXC91231_PASS_1()) {
  1080. /*
  1081. * Due to HW issue with LFDF dividers, to get 266MHz, PLL is
  1082. * relocked to 266MHz and ARM:AHB:IPG dividers are set to
  1083. * 1:2:4
  1084. */
  1085. mxc_pm_calc_mf_lfs(266);
  1086. if (voltage == HI_VOLT) {
  1087. mxc_pm_chgvoltage(LO_VOLT);
  1088. }
  1089.  
  1090. /* Change ARM:AHB:IPG divider ratio as 1:2:4 */
  1091. __raw_writel(((__raw_readl(MXC_CRMAP_ACDR) & ACDR_MASK)
  1092. | ARM_AHB_IPG_RATIO_266), MXC_CRMAP_ACDR);
  1093. return 0;
  1094. }
  1095.  
  1096. /*
  1097. * There are two conditions,
  1098. * 1. You have to be at Hi voltage to set DFS dividers
  1099. * 2. If not at Hi voltage, then move to Hi voltage and
  1100. * then set the dividers
  1101. */
  1102. if (voltage == LO_VOLT) {
  1103. /* First change frequency to 532 */
  1104. mxc_pm_chgfreq(CORE_532);
  1105. }
  1106.  
  1107. /* Configure scaling type to Integer scaling - to use DFS dividers */
  1108. mxc_pm_config_scale(DFS_ENABLE);
  1109.  
  1110. /* Set LFDF to LFDF_2 so that LFDF:ARM:AHB:IPG is 2:1:2:4 */
  1111. mxc_pm_setlfdf(MXC_CRMAP_ADCR_LFDF_2);
  1112.  
  1113. /* Reduce Voltage */
  1114. mxc_pm_chgvoltage(LO_VOLT);
  1115.  
  1116. break;
  1117.  
  1118. case CORE_399:
  1119. /* PLL RELOCKING */
  1120. /*
  1121. * if DFS_DIV_EN = 0 and LOW voltage implies core is running at
  1122. * 399MHz only on MXC91231 P2. And, 399 or 133 or 266
  1123. * on MXC91231 P1 due to workaround for HW issues and LFS PLL
  1124. * registers may be at 266MHz
  1125. */
  1126. if ((dfs_div == DFS_DISABLE) && (voltage == LO_VOLT)) {
  1127.  
  1128. /* CRM workaround on MXC91231 P1 */
  1129. if (CRM_ISSUE && MXC91231_PASS_1()) {
  1130. /*
  1131. * This implies either the core frequency is
  1132. * is already at 133MHz or 266MHz or 399MHz and
  1133. * the ratio will be at 1:3:6
  1134. */
  1135. __raw_writel(((__raw_readl(MXC_CRMAP_ACDR) &
  1136. ACDR_MASK) |
  1137. ARM_AHB_IPG_RATIO_LO),
  1138. MXC_CRMAP_ACDR);
  1139. mxc_pm_calc_mf_lfs(399);
  1140. }
  1141. return 0;
  1142. } else {
  1143. if (voltage == LO_VOLT) {
  1144. /*
  1145. * Raise voltage to HIGH voltage as the core is at
  1146. * either 133MHz or 266MHz using Integer scaling which.
  1147. * implies DFS_DIV_EN bit is set. So, to clear DFS_DIV_EN bit
  1148. * move to Hi voltage as this bit cannot be changed at Lo voltage
  1149. */
  1150. mxc_pm_chgfreq(CORE_532);
  1151. }
  1152.  
  1153. /* Now core is at Hi voltage */
  1154. /* Configure scaling type ALT_PLL and clear DFS_DIV_EN bit */
  1155. mxc_pm_config_scale(DFS_DISABLE);
  1156.  
  1157. /* CRM workaround on MXC91231 P1 */
  1158. if (CRM_ISSUE && MXC91231_PASS_1()) {
  1159. /*
  1160. * Set ARM divider to 2. So that ARM:AHB:IPG
  1161. * will be 2:4:8
  1162. */
  1163. __raw_writel(((__raw_readl(MXC_CRMAP_ACDR) &
  1164. ACDR_MASK) |
  1165. ARM_AHB_IPG_CRMRATIO_532),
  1166. MXC_CRMAP_ACDR);
  1167. }
  1168.  
  1169.  
  1170. /* Now, decrease the voltage */
  1171. mxc_pm_chgvoltage(LO_VOLT);
  1172.  
  1173. /*
  1174. * Wait until PLL relocks as DFS_DIV_EN bit is cleared and
  1175. * voltage has been decreased
  1176. */
  1177. while ((__raw_readl(PLL0_DP_CTL) & MXC_PLL_DP_CTL_LRF)
  1178. != MXC_PLL_DP_CTL_LRF) ;
  1179. /* CRM workaround on MXC91231 P1 */
  1180. if (CRM_ISSUE && MXC91231_PASS_1()) {
  1181. /*
  1182. * Reprogram PLL as LFS registers may be
  1183. * programmed to 266MHz
  1184. */
  1185. mxc_pm_calc_mf_lfs(399);
  1186. /*
  1187. * Set ARM divider to 2. So that ARM:AHB:IPG
  1188. * will be 2:3:6
  1189. */
  1190. __raw_writel(((__raw_readl(MXC_CRMAP_ACDR) &
  1191. ACDR_MASK) |
  1192. ARM_AHB_IPG_CRMRATIO_399),
  1193. MXC_CRMAP_ACDR);
  1194. }
  1195.  
  1196. /* Change ARM:AHB:IPG divider ratio as 1:3:6 */
  1197. __raw_writel(((__raw_readl(MXC_CRMAP_ACDR) & ACDR_MASK)
  1198. | ARM_AHB_IPG_RATIO_LO), MXC_CRMAP_ACDR);
  1199. }
  1200.  
  1201. break;
  1202.  
  1203. case CORE_532:
  1204. /* if DFS_DIV_EN = 1 and LOW voltage: 133 or 266 -> 532 */
  1205. if ((dfs_div == DFS_ENABLE) && (voltage == LO_VOLT)) {
  1206. /* This implies core is at 133 or 266 on P2 */
  1207. /* CRM workaround on MXC91231 P1 */
  1208. if (CRM_ISSUE && MXC91231_PASS_1()) {
  1209. /*
  1210. * Set ARM divider to 2. So that ARM:AHB:IPG
  1211. * will be 2:2:4
  1212. */
  1213. __raw_writel(((__raw_readl(MXC_CRMAP_ACDR) &
  1214. ACDR_MASK) |
  1215. ARM_AHB_IPG_CRMRATIO_266),
  1216. MXC_CRMAP_ACDR);
  1217. }
  1218.  
  1219. mxc_pm_chgvoltage(HI_VOLT);
  1220.  
  1221. } else if ((dfs_div == DFS_DISABLE) && (voltage == LO_VOLT)) {
  1222. /*
  1223. * This implies core is at 399 on P2 and 133 or 266 or 399
  1224. * on P1
  1225. */
  1226.  
  1227. /* CRM workaround on MXC91231 P1 */
  1228. if (CRM_ISSUE && MXC91231_PASS_1()) {
  1229. /*
  1230. * Now set the divider ratio to 2:2:4 suitable for
  1231. * 532MHz
  1232. */
  1233. __raw_writel(((__raw_readl(MXC_CRMAP_ACDR) &
  1234. ACDR_MASK) |
  1235. ARM_AHB_IPG_CRMRATIO_266),
  1236. MXC_CRMAP_ACDR);
  1237. } else {
  1238. /* Change ARM:AHB:IPG divider ratio as 1:4:8 */
  1239. __raw_writel(((__raw_readl(MXC_CRMAP_ACDR) &
  1240. ACDR_MASK) |
  1241. ARM_AHB_IPG_RATIO_HI),
  1242. MXC_CRMAP_ACDR);
  1243. }
  1244. /* Now, raise the core voltage */
  1245. mxc_pm_chgvoltage(HI_VOLT);
  1246.  
  1247. /* Configure the scaling type - not use DFS dividers */
  1248. mxc_pm_config_scale(DFS_DISABLE);
  1249.  
  1250. /*
  1251. * Wait until PLL relocks as DFS_DIV_EN bit is cleared and
  1252. * voltage has been increased
  1253. */
  1254. while ((__raw_readl(PLL0_DP_CTL) & MXC_PLL_DP_CTL_LRF)
  1255. != MXC_PLL_DP_CTL_LRF) ;
  1256.  
  1257. } else if (voltage == HI_VOLT) {
  1258. /* do nothing */
  1259. }
  1260.  
  1261. /* CRM workaround */
  1262. if ((CRM_ISSUE && MXC91231_PASS_1()) &&
  1263. (NO_SDRAMC_RATIO_ISSUE == 1)) {
  1264. /* Change ARM:AHB:IPG divider ratio as 1:4:8 */
  1265. __raw_writel(((__raw_readl(MXC_CRMAP_ACDR) & ACDR_MASK)
  1266. | ARM_AHB_IPG_RATIO_HI), MXC_CRMAP_ACDR);
  1267. }
  1268.  
  1269. break;
  1270.  
  1271. default:
  1272. return -ERR_FREQ_INVALID;
  1273. break;
  1274. }
  1275. return 0;
  1276. #endif /* CONFIG_MOT_FEAT_PM */
  1277. }
  1278.  
  1279. /*!
  1280. * To change AP core frequency and/or voltage suitably
  1281. *
  1282. * @param armfreq The desired ARM frequency
  1283. * @param ahbfreq The desired AHB frequency: constant value 133 MHz
  1284. * @param ipfreq The desired IP frequency : constant value 66.5 MHz
  1285. *
  1286. * @return Returns -ERR_FREQ_INVALID on failure
  1287. * Returns 0 on success
  1288. */
  1289. int mxc_pm_dvfs(unsigned long armfreq, long ahbfreq, long ipfreq)
  1290. {
  1291. int ret_val = -1;
  1292. dvfs_op_point_t dvfs_op_point = -1;
  1293. unsigned long flags;
  1294.  
  1295. /* Acquiring Lock */
  1296. spin_lock_irqsave(&dvfs_lock, flags);
  1297.  
  1298. switch (armfreq / MEGA_HERTZ) {
  1299.  
  1300. case CORE_133:
  1301. dvfs_op_point = CORE_133;
  1302. break;
  1303.  
  1304. case CORE_266:
  1305. dvfs_op_point = CORE_266;
  1306. break;
  1307.  
  1308. case CORE_399:
  1309. dvfs_op_point = CORE_399;
  1310. break;
  1311.  
  1312. case CORE_532:
  1313. dvfs_op_point = CORE_532;
  1314. break;
  1315.  
  1316. default:
  1317. /* Releasing lock */
  1318. spin_unlock_irqrestore(&dvfs_lock, flags);
  1319. return -ERR_FREQ_INVALID;
  1320. break;
  1321. }
  1322.  
  1323. ret_val = mxc_pm_chgfreq(dvfs_op_point);
  1324.  
  1325. /* Releasing lock */
  1326. spin_unlock_irqrestore(&dvfs_lock, flags);
  1327.  
  1328. return ret_val;
  1329. }
  1330.  
  1331. /*!
  1332. * Implementing steps required to transition to low-power modes
  1333. *
  1334. * @param mode The desired low-power mode. Possible values are,
  1335. * WAIT_MODE, STOP_MODE or DSM_MODE
  1336. *
  1337. */
  1338. void mxc_pm_lowpower(int mode)
  1339. {
  1340. unsigned int crm_ctrl, ctrl_slp;
  1341. #ifdef CONFIG_MOT_FEAT_PM
  1342. unsigned int ascsr, pll0_dp_ctlreg, pll1_dp_ctlreg;
  1343. unsigned int arm_ahb_ip_ratio = 0;
  1344. unsigned int apra = 0;
  1345. unsigned int aprb = 0;
  1346. unsigned int acder1 = 0;
  1347. unsigned int acder2 = 0;
  1348. unsigned int crmcom_cscr = 0;
  1349. #endif /* CONFIG_MOT_FEAT_PM */
  1350. #ifdef CONFIG_MOT_FEAT_PM_STATS
  1351. u32 avic_nipndh;
  1352. u32 avic_nipndl;
  1353. u32 rtc_before = 0;
  1354. u32 rtc_after = 0;
  1355. mpm_test_point_t exit_test_point = 0;
  1356. #endif
  1357.  
  1358. #ifdef CONFIG_MOT_WFN478
  1359. unsigned long flags;
  1360. #endif
  1361.  
  1362. if ((__raw_readl(AVIC_VECTOR) & MXC_WFI_ENABLE) == 0) {
  1363. /*
  1364. * If JTAG is connected then WFI is not enabled
  1365. * So return
  1366. */
  1367. return;
  1368. }
  1369.  
  1370. /* Check parameter */
  1371. if ((mode != WAIT_MODE) && (mode != STOP_MODE) && (mode != DSM_MODE)) {
  1372. return;
  1373. }
  1374.  
  1375. #ifdef CONFIG_MOT_WFN478
  1376. local_irq_save(flags);
  1377. #else
  1378. local_irq_disable();
  1379. #endif
  1380.  
  1381. switch (mode) {
  1382. case WAIT_MODE:
  1383. /* Writing '01' to CRM_lpmd bits */
  1384. crm_ctrl =
  1385. (__raw_readl(MXC_DSM_CRM_CONTROL) &
  1386. ~(MXC_DSM_CRM_CTRL_LPMD1)) | (MXC_DSM_CRM_CTRL_LPMD0);
  1387. __raw_writel(crm_ctrl, MXC_DSM_CRM_CONTROL);
  1388. #ifdef CONFIG_MOT_FEAT_PM_STATS
  1389. exit_test_point = MPM_TEST_WAIT_EXIT;
  1390. #endif
  1391. break;
  1392.  
  1393. case STOP_MODE:
  1394. /*
  1395. * High-Level Power Management should ensure all devices are
  1396. * turned-off before entering STOP mode. This will ensure
  1397. * that all acknowledgements (MXC_CRMAP_AMCR) are bypassed else STOP mode
  1398. * will not be entered
  1399. */
  1400.  
  1401. /* Disable Timer interrupt source */
  1402. __raw_writel((__raw_readl(LO_INTR_EN) & AVIC_TIMER_INTR_DIS),
  1403. LO_INTR_EN);
  1404.  
  1405. /* Writing '00' to CRM_lpmd bits */
  1406. crm_ctrl =
  1407. (__raw_readl(MXC_DSM_CRM_CONTROL) &
  1408. ~(MXC_DSM_CRM_CTRL_LPMD1)) & (~MXC_DSM_CRM_CTRL_LPMD0);
  1409. __raw_writel(crm_ctrl, MXC_DSM_CRM_CONTROL);
  1410. #ifdef CONFIG_MOT_FEAT_PM_STATS
  1411. exit_test_point = MPM_TEST_STOP_EXIT;
  1412. #endif
  1413. break;
  1414.  
  1415. case DSM_MODE:
  1416. /*
  1417. * High-Level Power Management should ensure all devices are
  1418. * turned-off before entering DSM mode. This will ensure
  1419. * that all acknowledgements (MXC_CRMAP_AMCR) are bypassed else DSM mode
  1420. * will not be entered
  1421. */
  1422.  
  1423. #ifdef CONFIG_MOT_FEAT_PM
  1424. /*
  1425. * Store RUN mode settings and apply aggressive clock
  1426. * gating for STOP mode.
  1427. */
  1428. apra = __raw_readl(MXC_CRMAP_APRA);
  1429. aprb = __raw_readl(MXC_CRMAP_APRB);
  1430. acder1 = __raw_readl(MXC_CRMAP_ACDER1);
  1431. acder2 = __raw_readl(MXC_CRMAP_ACDER2);
  1432.  
  1433. __raw_writel((apra & ~APRA_ALL_CLK_EN), MXC_CRMAP_APRA);
  1434. __raw_writel((aprb & ~APRB_ALL_CLK_EN), MXC_CRMAP_APRB);
  1435. __raw_writel((acder1 & ~ACDER1_ALL_CLK_EN), MXC_CRMAP_ACDER1);
  1436. __raw_writel((acder2 & ~ACDER2_ALL_CLK_EN), MXC_CRMAP_ACDER2);
  1437. #endif /* CONFIG_MOT_FEAT_PM */
  1438.  
  1439. /* Enable WellBias */
  1440. __raw_writel((__raw_readl(MXC_CRMAP_AMCR) | ENABLE_WELL_BIAS),
  1441. MXC_CRMAP_AMCR);
  1442.  
  1443. #ifdef CONFIG_MOT_FEAT_ACTIVE_AND_LOW_POWER_INTERVAL_TIMERS
  1444. /* Enable EPIT Interrupt */
  1445. __raw_writel((__raw_readl(LO_INTR_EN) | (1<<28)), LO_INTR_EN);
  1446. /* Disable GPT interrupt source */
  1447. __raw_writel((__raw_readl(LO_INTR_EN) & 0xDFFFFFFF), LO_INTR_EN);
  1448. #else
  1449. /* Disable Timer interrupt source */
  1450. __raw_writel((__raw_readl(LO_INTR_EN) & AVIC_TIMER_INTR_DIS),
  1451. LO_INTR_EN);
  1452. #endif
  1453.  
  1454. #ifdef CONFIG_MOT_FEAT_PM
  1455. /*** Current Drain Improvement ***/
  1456. if (!mxc_pm_ddram_detected() && pll0_off_in_ap_dsm()) {
  1457. /*** ONLY IF THE MEMORY IS NOT A DDRAM ***/
  1458.  
  1459. /* Switch AP domain to DSP PLL (PLL1) */
  1460.  
  1461. /*
  1462. * Set PPD1 bit in CRM_COM CSCR to prevent
  1463. * PLL1 off if BP only is in DSM.
  1464. */
  1465. crmcom_cscr = __raw_readl(MXC_CRMCOM_CSCR);
  1466. __raw_writel((crmcom_cscr | CRM_COM_CSCR_PPD1), MXC_CRMCOM_CSCR);
  1467.  
  1468. /*
  1469. * Re-enable and Restart PLL1.
  1470. * We don't use the mxc_pll_request_pll
  1471. * service because we don't know the value of
  1472. * the counter. We have to ensure that we
  1473. * restart and relock the PLL, so we just do
  1474. * it.
  1475. */
  1476. if ((__raw_readl(pll_dp_ctlreg[DSPPLL]) & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF)
  1477. {
  1478. pll1_dp_ctlreg = ((__raw_readl(pll_dp_ctlreg[DSPPLL]) |
  1479. MXC_PLL_DP_CTL_RST) | MXC_PLL_DP_CTL_UPEN);
  1480. __raw_writel(pll1_dp_ctlreg, pll_dp_ctlreg[DSPPLL]);
  1481. }
  1482.  
  1483. /* Wait until PLL1 is locked */
  1484. while((__raw_readl(pll_dp_ctlreg[DSPPLL]) & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
  1485.  
  1486. /* Switch AP domain to PLL1. */
  1487. ascsr = ((__raw_readl(MXC_CRMAP_ASCSR) & ~ASCSR_APSEL_1) | ASCSR_APSEL_0);
  1488. __raw_writel(ascsr, MXC_CRMAP_ASCSR);
  1489. udelay(1);
  1490.  
  1491. /* Unlock PLL0 */
  1492. pll0_dp_ctlreg = ((__raw_readl(pll_dp_ctlreg[MCUPLL]) &
  1493. ~MXC_PLL_DP_CTL_RST) & ~MXC_PLL_DP_CTL_UPEN);
  1494. __raw_writel(pll0_dp_ctlreg, pll_dp_ctlreg[MCUPLL]);
  1495.  
  1496. /*
  1497. * Force ARM:AHB:IP ratio to have
  1498. * SDRAM clock = PLL1 / 2
  1499. * Save the existing ratio so we can restore
  1500. * it after we wake up.
  1501. *
  1502. * We are about to switch to PLL1 (DSPPLL)
  1503. * while we are in DSM so we can turn off
  1504. * PLL0 (MCUPLL). We set the PLL dividers to
  1505. * 1:2:4 because it satisfies the requirements
  1506. * that SDRAM is <= 133Mhz and the SDRAM:IP
  1507. * frequency is 2:1 for all PLL0 frequencies
  1508. * that we use (266/399/532) *and* the PLL1
  1509. * frequency (156Mhz).
  1510. */
  1511. arm_ahb_ip_ratio = __raw_readl(MXC_CRMAP_ACDR);
  1512.  
  1513. if (cur_dvfs_op_point_index == INDX_133) {
  1514. /*
  1515. * If we get here, then we are currently operating at
  1516. * the 133 operating point.
  1517. *
  1518. * Note that all operating points except 133 use a
  1519. * CPU divider ratio of 1, so the switch can be done
  1520. * in one step.
  1521. *
  1522. * Freescale recommends that moving from a divider
  1523. * ratio of 2:1:2 (for operating point 133) should be
  1524. * done in two steps. The first step is 2:2:4.
  1525. *
  1526. * We delay after we write to ensure that the dividers
  1527. * are propagated in the correct order. We are
  1528. * running now at 2:1:2. We move to 2:2:4 which
  1529. * changes only the AHB/IPG dividers. Then we make
  1530. * the final change which changes the CPU divider.
  1531. *
  1532. * Failure to accomplish the divider ratio switch
  1533. * in two steps results in system instability.
  1534. */
  1535. __raw_writel(ARM_AHB_IPG_RATIO_224, MXC_CRMAP_ACDR);
  1536. udelay(1);
  1537. }
  1538. __raw_writel(ARM_AHB_IPG_RATIO_124, MXC_CRMAP_ACDR);
  1539.  
  1540. /*
  1541. * Restore the CRM_COM CSCR. This deasserts
  1542. * the PPD1 bit in CRM_COM CSCR to allow PLL1
  1543. * off if BP only is in DSM.
  1544. */
  1545. __raw_writel(crmcom_cscr, MXC_CRMCOM_CSCR);
  1546. }
  1547.  
  1548. /*
  1549. * Force external interrupts to be delayed 5 CKIL clock cycles
  1550. * while in DSM DEEPSLEEP1 state.
  1551. */
  1552. __raw_writel(MXC_DSM_MGPER_EN_MGFX | MXC_DSM_MGPER_PER(5),
  1553. MXC_DSM_MGPER);
  1554.  
  1555.  
  1556. /* Reset counter block - Start go_to_sleep transition with COUNT32 = 0 */
  1557. __raw_writel((__raw_readl(MXC_DSM_CONTROL1) | MXC_CONTROL1_RST_CNT32),
  1558. MXC_DSM_CONTROL1);
  1559. #endif /* CONFIG_MOT_FEAT_PM */
  1560.  
  1561. /* Enable DSM */
  1562. __raw_writel((__raw_readl(MXC_DSM_CONTROL0) |
  1563. MXC_DSM_CONTROL0_MSTR_EN), MXC_DSM_CONTROL0);
  1564.  
  1565. /* Enable SLEEP and WAKE UP DISABLE */
  1566. ctrl_slp =
  1567. ((__raw_readl(MXC_DSM_CONTROL1) | MXC_DSM_CONTROL1_SLEEP) |
  1568. MXC_DSM_CONTROL1_WAKEUP_DISABLE);
  1569. __raw_writel(ctrl_slp, MXC_DSM_CONTROL1);
  1570.  
  1571. #ifndef CONFIG_MOT_FEAT_PM
  1572. /* COUNT32 must not be reset between two DSM state machine transitions */
  1573. if (CONFIG_RESET_COUNT32) {
  1574. /* Set RST_COUNT32_EN bit */
  1575. __raw_writel((__raw_readl(MXC_DSM_CONTROL1) |
  1576. MXC_DSM_CONTROL1_RST_CNT32_EN),
  1577. MXC_DSM_CONTROL1);
  1578. }
  1579. #endif
  1580.  
  1581. /* Set STBY_COMMIT_EN bit */
  1582. __raw_writel((__raw_readl(MXC_DSM_CONTROL0) |
  1583. MXC_DSM_CONTROL0_STBY_COMMIT_EN),
  1584. MXC_DSM_CONTROL0);
  1585.  
  1586. #ifndef CONFIG_MOT_FEAT_PM
  1587. /* L1T is owned by BP => AP does not need to restart it */
  1588. /* AP DSM state machine looping between LOCKED and WAIT4SLEEP states */
  1589. /* Set RESTART bit */
  1590. __raw_writel((__raw_readl(MXC_DSM_CONTROL0) |
  1591. MXC_DSM_CONTROL0_RESTART), MXC_DSM_CONTROL0);
  1592. #endif
  1593.  
  1594. /* Setting SLEEP time */
  1595. __raw_writel(SLEEP_TIME, MXC_DSM_SLEEP_TIME);
  1596.  
  1597. /* Setting WARMPER and LOCKPER */
  1598. __raw_writel(CALC_WAKE_TIME, MXC_DSM_WARM_PER);
  1599. __raw_writel(CALC_LOCK_TIME, MXC_DSM_LOCK_PER);
  1600.  
  1601. __raw_writel((__raw_readl(MXC_DSM_CTREN) | MXC_DSM_CTREN_CNT32),
  1602. MXC_DSM_CTREN);
  1603.  
  1604. /* Writing '00' to CRM_lpmd bits */
  1605. crm_ctrl =
  1606. (__raw_readl(MXC_DSM_CRM_CONTROL) &
  1607. (~MXC_DSM_CRM_CTRL_LPMD1)) & (~MXC_DSM_CRM_CTRL_LPMD0);
  1608. __raw_writel(crm_ctrl, MXC_DSM_CRM_CONTROL);
  1609.  
  1610. #ifdef CONFIG_MOT_FEAT_PM_STATS
  1611. MPM_REPORT_TEST_POINT(1, MPM_TEST_DSM_ENTER);
  1612. exit_test_point = MPM_TEST_DSM_EXIT;
  1613. #endif
  1614. break;
  1615. }
  1616. #ifdef CONFIG_MOT_FEAT_PM_STATS
  1617. /* Read the clock before we go to wait/stop/dsm. */
  1618. rtc_before = rtc_sw_get_internal_ticks();
  1619. #endif /* CONFIG_MOT_FEAT_PM_STATS */
  1620.  
  1621. /* Executing CP15 (Wait-for-Interrupt) Instruction */
  1622. cpu_do_idle();
  1623.  
  1624. #ifdef CONFIG_MOT_FEAT_PM_STATS
  1625. rtc_after = rtc_sw_get_internal_ticks();
  1626.  
  1627. /*
  1628. * Retrieve the pending interrupts. These are the
  1629. * interrupt(s) that woke us up.
  1630. */
  1631. avic_nipndh = __raw_readl(AVIC_NIPNDH);
  1632. avic_nipndl = __raw_readl(AVIC_NIPNDL);
  1633. #endif
  1634.  
  1635.  
  1636. #ifdef CONFIG_MOT_FEAT_PM
  1637. switch (mode) {
  1638. case WAIT_MODE:
  1639. case STOP_MODE:
  1640. break;
  1641.  
  1642. case DSM_MODE:
  1643. /* Reset DSM controller upon wakeup. */
  1644.  
  1645. /* Clear sleep bit */
  1646. __raw_writel(__raw_readl(MXC_DSM_CONTROL1)
  1647. & (~MXC_DSM_CONTROL1_SLEEP), MXC_DSM_CONTROL1);
  1648.  
  1649. /* Reset Counter Block and State Machine */
  1650. __raw_writel(__raw_readl(MXC_DSM_CONTROL1)
  1651. | MXC_DSM_CONTROL1_CB_RST | MXC_DSM_CONTROL1_SM_RST,
  1652. MXC_DSM_CONTROL1);
  1653.  
  1654. /* Wait for CB and SM reset bits to clear */
  1655. while((__raw_readl(MXC_DSM_CONTROL1)
  1656. & (MXC_DSM_CONTROL1_CB_RST | MXC_DSM_CONTROL1_SM_RST))
  1657. != 0x00) {
  1658. /* spin */
  1659. }
  1660.  
  1661. /* Disable MGPER */
  1662. __raw_writel(__raw_readl(MXC_DSM_MGPER)
  1663. & (~MXC_DSM_MGPER_EN_MGFX), MXC_DSM_MGPER);
  1664.  
  1665. /* End reset of DSM controller. */
  1666.  
  1667. /*** Current Drain Improvement ***/
  1668. /*** ONLY IF THE MEMORY IS NOT A DDRAM ***/
  1669. if (!mxc_pm_ddram_detected() && pll0_off_in_ap_dsm()) {
  1670. /* Restore ARM:AHB:IP ratio */
  1671. if (cur_dvfs_op_point_index == INDX_133) {
  1672. /*
  1673. * If we get here, then we are switching to the 133
  1674. * operating point.
  1675. *
  1676. * Freescale recommends that going to a divider ratio
  1677. * of 2:1:2 (for operating point 133) should be done
  1678. * in two steps. The first step is 2:2:4.
  1679. *
  1680. * Note that all operating points except 133 use a
  1681. * CPU divider ratio of 1, so the switch can be done
  1682. * in one step.
  1683. *
  1684. * We delay after we write to ensure that the dividers
  1685. * are propagated in the correct order. We are
  1686. * running now at 1:2:4. We move to 2:2:4 which
  1687. * changes only the CPU divider. Then we make the
  1688. * final change which changes the AHB/IPG dividers.
  1689. *
  1690. * Failure to accomplish the divider ratio switch
  1691. * in two steps results in system instability.
  1692. */
  1693. __raw_writel(ARM_AHB_IPG_RATIO_224, MXC_CRMAP_ACDR);
  1694. udelay(1);
  1695. }
  1696. __raw_writel(arm_ahb_ip_ratio, MXC_CRMAP_ACDR);
  1697.  
  1698.  
  1699. /*
  1700. * Re-enable and Restart PLL0.
  1701. * We don't use the mxc_pll_request_pll
  1702. * service because we don't know the value of
  1703. * the counter. We have to ensure that we
  1704. * restart and relock the PLL, so we just do
  1705. * it.
  1706. */
  1707. pll0_dp_ctlreg = ((__raw_readl(pll_dp_ctlreg[MCUPLL]) |
  1708. MXC_PLL_DP_CTL_RST) | MXC_PLL_DP_CTL_UPEN);
  1709. __raw_writel(pll0_dp_ctlreg, pll_dp_ctlreg[MCUPLL]);
  1710.  
  1711. /* Wait until PLL relocks */
  1712. while((__raw_readl(pll_dp_ctlreg[MCUPLL]) &
  1713. MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
  1714.  
  1715. /* Switch AP domain back on PLL0 */
  1716. ascsr = ((__raw_readl(MXC_CRMAP_ASCSR) & ~ASCSR_APSEL_0) &
  1717. ~ASCSR_APSEL_1);
  1718. __raw_writel(ascsr, MXC_CRMAP_ASCSR);
  1719.  
  1720. /*
  1721. * Deassert PPD1 bit in CRM_COM CSCR to allow PLL1 off
  1722. * if BP only is in DSM
  1723. */
  1724. __raw_writel((__raw_readl(MXC_CRMCOM_CSCR) &
  1725. ~CRM_COM_CSCR_PPD1), MXC_CRMCOM_CSCR);
  1726. }
  1727.  
  1728. /* Restore RUN mode clock gating */
  1729. __raw_writel(apra, MXC_CRMAP_APRA);
  1730. __raw_writel(aprb, MXC_CRMAP_APRB);
  1731. __raw_writel(acder1, MXC_CRMAP_ACDER1);
  1732. __raw_writel(acder2, MXC_CRMAP_ACDER2);
  1733. break;
  1734. }
  1735. /*** Current Drain Improvement - END ***/
  1736. #endif
  1737.  
  1738. /* Enable timer interrupt */
  1739. __raw_writel((__raw_readl(LO_INTR_EN) | AVIC_TIMER_INTR_EN),
  1740. LO_INTR_EN);
  1741.  
  1742. #ifdef CONFIG_MOT_WFN478
  1743. local_irq_restore(flags);
  1744. #else
  1745. local_irq_enable();
  1746. #endif
  1747.  
  1748. #if defined(CONFIG_MOT_DSM_INDICATOR) || defined(CONFIG_MOT_TURBO_INDICATOR)
  1749. printk("MPM: restore from sleep,exit_test_point=%d, rtc_before = 0x%x, rtc_after= 0x%x, pending_interrupt=0x%x,0x%x\n",
  1750. exit_test_point, rtc_before, rtc_after, avic_nipndl, avic_nipndh);
  1751.  
  1752. #endif
  1753.  
  1754.  
  1755. #ifdef CONFIG_MOT_FEAT_PM_STATS
  1756. MPM_REPORT_TEST_POINT(5, exit_test_point, rtc_before, rtc_after,
  1757. avic_nipndl, avic_nipndh);
  1758. #endif
  1759. }
  1760.  
  1761. /*!
  1762. * Enables acknowledgement from module when entering stop or DSM mode.
  1763. *
  1764. * @param ack The desired module acknowledgement to enable.
  1765. *
  1766. */
  1767. void mxc_pm_lp_ack_enable(int ack)
  1768. {
  1769. /* Clear selected bypass and enable the acknowledgement */
  1770. __raw_writel(__raw_readl(MXC_CRMAP_AMCR) & ~(ack << 16),
  1771. MXC_CRMAP_AMCR);
  1772. }
  1773.  
  1774. /*!
  1775. * Disables acknowledgement from module when entering stop or DSM mode.
  1776. *
  1777. * @param ack The desired module acknowledgement to disable.
  1778. *
  1779. */
  1780. void mxc_pm_lp_ack_disable(int ack)
  1781. {
  1782. /* Set selected bypass and disable the acknowledgement */
  1783. __raw_writel(__raw_readl(MXC_CRMAP_AMCR) | (ack << 16), MXC_CRMAP_AMCR);
  1784. }
  1785.  
  1786. /*!
  1787. * Implementing Level 1 CRM Gate Control. Level 2 gate control
  1788. * is provided at module level using LPMD registers
  1789. *
  1790. * @param group The desired clock gate control register bits.
  1791. * Possible values are 0 through 6
  1792. * @param opt The desired option requesting clock to run during stop
  1793. * and wait modes or just during the stop mode. Possible
  1794. * values are GATE_STOP_WAIT and GATE_STOP.
  1795. *
  1796. */
  1797. void mxc_pm_clockgate(int group, int opt)
  1798. {
  1799. if (opt == GATE_STOP_WAIT) {
  1800. __raw_writel(((__raw_readl(MXC_CRMAP_ACGCR) &
  1801. (~gate_run[group])) | (gate_stop_wait[group])),
  1802. MXC_CRMAP_ACGCR);
  1803. } else if (opt == GATE_STOP) {
  1804. __raw_writel(((__raw_readl(MXC_CRMAP_ACGCR) &
  1805. (~gate_run[group])) | (gate_stop[group])),
  1806. MXC_CRMAP_ACGCR);
  1807. }
  1808. }
  1809.  
  1810. /*
  1811. * This API is not supported on MXC91231
  1812. */
  1813. int mxc_pm_intscale(long armfreq, long ahbfreq, long ipfreq)
  1814. {
  1815. return -MXC_PM_API_NOT_SUPPORTED;
  1816. }
  1817.  
  1818. /*
  1819. * This API is not supported on MXC91231
  1820. */
  1821. int mxc_pm_pllscale(long armfreq, long ahbfreq, long ipfreq)
  1822. {
  1823. return -MXC_PM_API_NOT_SUPPORTED;
  1824. }
  1825.  
  1826. #ifndef CONFIG_MOT_FEAT_PM
  1827. /*!
  1828. * Programming MCUPLL HFS register after lvs and HFSM signals are
  1829. * synchronised
  1830. */
  1831. static void mxc_pm_config_hfs(void)
  1832. {
  1833. /*
  1834. * When core is running at 399MHz and HFSM bit is
  1835. * synchronised with lvs signal, then HFS register can
  1836. * configured to 532MHz
  1837. */
  1838. __raw_writel(DP_HFS_OP, PLL0_DP_HFSOP);
  1839. __raw_writel(DP_HFS_MFN, PLL0_DP_HFSMFN);
  1840. __raw_writel(DP_HFS_MFD, PLL0_DP_HFSMFD);
  1841. }
  1842.  
  1843. /*!
  1844. * This function is used to synchronise HFSM bit and the LVS signal.
  1845. * They are out of sync by default. So, moving to hi voltage
  1846. * using Int DVFS fixes this
  1847. *
  1848. */
  1849. static void mxc_pm_hfsm_sync(void)
  1850. {
  1851. /*
  1852. * HFSM bit gets synchronised with LVS after the initial low to high
  1853. * Integer DVFS
  1854. */
  1855. unsigned long adcr_val;
  1856.  
  1857. /* Set up to do integer DVFS low to High */
  1858. adcr_val =
  1859. ((__raw_readl(MXC_CRMAP_ADCR) & (~MXC_CRMAP_ADCR_ALT_PLL)) &
  1860. (~MXC_CRMAP_ADCR_DIV_BYP)) | (MXC_CRMAP_ADCR_DFS_DIVEN);
  1861. __raw_writel(adcr_val, MXC_CRMAP_ADCR);
  1862.  
  1863. /*
  1864. * Clear the DVFS_BYP bypass bit to allow voltage change.
  1865. */
  1866. __raw_writel((__raw_readl(MXC_DSM_CRM_CONTROL) &
  1867. (~MXC_DSM_CRM_CTRL_DVFS_BYP)), MXC_DSM_CRM_CONTROL);
  1868.  
  1869. /* Change voltage status */
  1870. mxc_pm_chgvoltage(HI_VOLT);
  1871.  
  1872. /* Reset to PLL Relock DVFS at Hi voltage */
  1873. adcr_val =
  1874. (((__raw_readl(MXC_CRMAP_ADCR) | (MXC_CRMAP_ADCR_DIV_BYP)) &
  1875. (~MXC_CRMAP_ADCR_DFS_DIVEN)) | (MXC_CRMAP_ADCR_CLK_ON)) &
  1876. (~MXC_CRMAP_ADCR_ALT_PLL);
  1877. __raw_writel(adcr_val, MXC_CRMAP_ADCR);
  1878.  
  1879. /* Resetting LFDF to divide by 1 */
  1880. mxc_pm_setlfdf(MXC_CRMAP_ADCR_LFDF_0);
  1881.  
  1882. /*
  1883. * Now HFSM and VSTAT are synchronised.
  1884. * So, moving back to low voltage using PLL scaling
  1885. */
  1886. mxc_pm_chgvoltage(LO_VOLT);
  1887.  
  1888. /*
  1889. * Configure HFS settings for 532MHz
  1890. */
  1891. mxc_pm_config_hfs();
  1892.  
  1893. }
  1894. #endif /* !CONFIG_MOT_FEAT_PM */
  1895.  
  1896. #ifdef CONFIG_MOT_FEAT_PM
  1897.  
  1898. /*
  1899. * PLLs dithering
  1900. */
  1901.  
  1902. /*!
  1903. * Dithering enable/disable of the AP and USB PLLs
  1904. * SCM-A11: only ap_core_normal_pll_ppm and ap_usb_pll_ppm are concerned.
  1905. * Must be called only if a non 0 ppm value has been setup via mxc_pm_dither_setup
  1906. *
  1907. * @param enable 0: disable, 1: enable
  1908. * @param pll_number of the type ap_pll_number_t: PLL to enable/disable
  1909. *
  1910. * @return 0 OK, -1 wrong PLL number
  1911. */
  1912. int mxc_pm_dither_control(int enable, enum plls pll_number)
  1913. {
  1914. int togc_val;
  1915.  
  1916. if ((pll_number != MCUPLL) && (pll_number != USBPLL))
  1917. return -1;
  1918.  
  1919. if (enable) {
  1920. togc_val = __raw_readl(pll_dp_mfn_togc[pll_number]) & ~TOG_DIS;
  1921. __raw_writel(togc_val, pll_dp_mfn_togc[pll_number]);
  1922. } else {
  1923. togc_val = __raw_readl(pll_dp_mfn_togc[pll_number]) | TOG_DIS;
  1924. __raw_writel(togc_val, pll_dp_mfn_togc[pll_number]);
  1925. }
  1926.  
  1927. return 0;
  1928. }
  1929.  
  1930.  
  1931. /*!
  1932. * Dithering: AP PLL dithering setup sequence
  1933. * SCM-A11: only ap_core_normal_pll_ppm and ap_usb_pll_ppm are concerned.
  1934. *
  1935. * @param pll_number of type enum ap_pll_number_t
  1936. * @param pll_mfn_values of type enum ap_pll_mfn_values_t* for storage of register values
  1937. *
  1938. * @return 0 OK, -1 wrong pll_number
  1939. */
  1940. static int mxc_pm_dither_pll_setup(enum plls pll_number,
  1941. ap_pll_mfn_values_t *ap_pll_mfn_values)
  1942. {
  1943. int reg_val;
  1944.  
  1945. if ((pll_number != MCUPLL) && (pll_number != USBPLL))
  1946. return -1;
  1947.  
  1948. /* Disable dithering */
  1949. mxc_pm_dither_control(0, pll_number);
  1950.  
  1951. /* Wait for end of the dithering cycle. */
  1952. while (__raw_readl(pll_dp_destat[pll_number]) & TOG_SEL);
  1953.  
  1954. /* Setup PLL registers */
  1955. __raw_writel(ap_pll_mfn_values->ap_pll_dp_hfs_mfnminus,
  1956. pll_dp_mfn_minus_reg[pll_number]);
  1957. __raw_writel(ap_pll_mfn_values->ap_pll_dp_hfs_mfnplus,
  1958. pll_dp_mfn_plus_reg[pll_number]);
  1959.  
  1960. /* Write toggle rate: TOG_CNT of TOGC register */
  1961. reg_val = __raw_readl(pll_dp_mfn_togc[pll_number]) & ~TOGC_CNT_MASK;
  1962. reg_val |= TOGC_CNT_VALUE;
  1963. __raw_writel(reg_val, pll_dp_mfn_togc[pll_number]);
  1964.  
  1965. /* Generate a load_req */
  1966. reg_val = __raw_readl(pll_dp_config[pll_number]) | DP_LDREQ;
  1967. __raw_writel(reg_val, pll_dp_config[pll_number]);
  1968.  
  1969. /* Enable dithering, only if ppm value != 0 */
  1970. if (ap_pll_mfn_values->ap_pll_ppm_value != 0)
  1971. mxc_pm_dither_control(1, pll_number);
  1972.  
  1973. return 0;
  1974. }
  1975.  
  1976.  
  1977. /*!
  1978. * Dithering: PLL dithering parameters calculation
  1979. * This function guarantees that if the calculations
  1980. * fail in any way (fcn return value is -1) then the
  1981. * pll_mfn_values structure is not modified.
  1982. * SCM-A11: only ap_core_normal_pll_ppm and ap_usb_pll_ppm are calculated.
  1983. *
  1984. * @param pll_ppm_value
  1985. * @param pll_number of type enum plls
  1986. * @param pll_mfn_values of type ap_pll_mfn_values_t* for storage of register values
  1987. *
  1988. * @return 0 OK, -1 calculated parameters out of range
  1989. */
  1990. static int mxc_pm_dither_calc_mfnplusminus(u16 pll_ppm_value,
  1991. enum plls pll_number,
  1992. ap_pll_mfn_values_t *pll_mfn_values)
  1993. {
  1994. u32 mfi_hfs, mfd_hfs;
  1995. s32 mfn_hfs;
  1996. s32 prod_hfs;
  1997. s64 var1_hfs;
  1998. s64 var2_hfs;
  1999. int ap_pll_hfs_mfnplus, ap_pll_hfs_mfnminus;
  2000.  
  2001. /* Compute MFNPLUS and MFNMINUS from registers value for HFS mode */
  2002. /* Use the MFI, MFN, and MFD values from the provided structure. */
  2003. mfi_hfs = (pll_mfn_values->ap_pll_dp_hfs_op >> 4) & 0xF;
  2004. mfd_hfs = pll_mfn_values->ap_pll_dp_hfs_mfd;
  2005. mfn_hfs = pll_mfn_values->ap_pll_dp_hfs_mfn;
  2006.  
  2007. /* Store the MFI*MFD product value */
  2008. prod_hfs = (s32)(mfi_hfs) * (s32)(mfd_hfs);
  2009.  
  2010. /* Compute MFNPLUS and MFNMINUS from MFN value for Normal Mode */
  2011. var1_hfs = (s64)(prod_hfs + mfn_hfs) * (s64)(1000000 + (pll_ppm_value));
  2012. var2_hfs = var1_hfs;
  2013.  
  2014. /* MFN_PLUS <=== (MFI*MFD + MFN)*(1+EpsilonPlus/1000000) - MFI*MFD */
  2015. do_div(var1_hfs, 1000000);
  2016. ap_pll_hfs_mfnplus = (s32)var1_hfs - prod_hfs;
  2017.  
  2018. /*
  2019. * MFN_MINUS <=== (MFI*MFD + MFN)*(1-EpsilonMinus/1000000) - MFI*MFD
  2020. * We could do the calculation above, but the calculation below is
  2021. * faster and equivalent.
  2022. */
  2023. ap_pll_hfs_mfnminus = (mfn_hfs * 2) - ap_pll_hfs_mfnplus;
  2024.  
  2025.  
  2026. /* Verify that MFN values are not out of bounds. */
  2027. if ( (DPLL_MFN_TO_ABSOLUTE(ap_pll_hfs_mfnplus) > mfd_hfs) ||
  2028. (DPLL_MFN_TO_ABSOLUTE(ap_pll_hfs_mfnminus) > mfd_hfs) )
  2029. {
  2030. return -1;
  2031. }
  2032.  
  2033. /* Only store the values if they are properly validated. */
  2034. pll_mfn_values->ap_pll_ppm_value = pll_ppm_value;
  2035. pll_mfn_values->ap_pll_dp_hfs_mfnplus = ap_pll_hfs_mfnplus;
  2036. pll_mfn_values->ap_pll_dp_hfs_mfnminus = ap_pll_hfs_mfnminus;
  2037.  
  2038. return 0;
  2039. }
  2040.  
  2041.  
  2042. /*!
  2043. * Dithering setup: pass the PLLs ppm values. This function calculates
  2044. * and stores the MFN+- values locally for the AP PLL,
  2045. * sets up the USB PLL dithering, and enables the dithering.
  2046. * SCM-A11: only ap_core_normal_pll_ppm and ap_usb_pll_ppm PLLs are used.
  2047. *
  2048. * @param ap_core_normal_pll_ppm ppm value of AP core PLL, normal mode
  2049. * @param ap_core_turbo_pll_ppm ppm value of AP core PLL, turbo mode
  2050. * @param ap_usb_pll_ppm ppm value of USB PLL
  2051. *
  2052. * @return Returns 0 on success, -1 on invalid ppm value(s)
  2053. */
  2054. int mxc_pm_dither_setup(u16 ap_core_normal_pll_ppm,
  2055. u16 ap_core_turbo_pll_ppm,
  2056. u16 ap_usb_pll_ppm)
  2057. {
  2058. unsigned long flags;
  2059. int rc = 0;
  2060. dvfs_op_point_t dvfs_op;
  2061. dvfs_op_point_index_t dvfs_op_index;
  2062.  
  2063. if (ap_core_normal_pll_ppm > MAX_PLL_PPM_VALUE)
  2064. return -1;
  2065.  
  2066. if (ap_usb_pll_ppm > MAX_PLL_PPM_VALUE)
  2067. return -1;
  2068.  
  2069. dvfs_op = mxc_get_clocks(CPU_CLK) / MEGA_HERTZ;
  2070.  
  2071. /* Acquiring Lock */
  2072. spin_lock_irqsave(&dvfs_lock, flags);
  2073.  
  2074. for (dvfs_op_index=INDX_FIRST; (rc==0) && (dvfs_op_index<NUM_DVFSOP_INDEXES); dvfs_op_index++)
  2075. {
  2076. /* AP normal PLL dithering setup: calc, storage, setup, enable */
  2077. /* Calc AP PLL MFN+- values for HFS mode */
  2078. rc = mxc_pm_dither_calc_mfnplusminus(ap_core_normal_pll_ppm,
  2079. MCUPLL,
  2080. &opinfo[dvfs_op_index]);
  2081.  
  2082. /* Setup AP PLL registers: MFN+-, toggle rate, Enable bit if ppm!=0 */
  2083. if ((rc == 0) && (dvfsop2index(dvfs_op) == dvfs_op_index)) {
  2084. rc = mxc_pm_dither_pll_setup(MCUPLL,
  2085. &opinfo[dvfs_op_index]);
  2086. }
  2087. }
  2088.  
  2089. /* AP USB PLL dithering setup: calc, storage, setup, enable */
  2090. if (rc == 0) {
  2091. /* Calc USB PLL MFN+- values for HFS mode */
  2092. rc = mxc_pm_dither_calc_mfnplusminus(ap_usb_pll_ppm,
  2093. USBPLL,
  2094. &ap_usb_pll_mfn_values);
  2095.  
  2096. /* Setup USB PLL registers: MFN+-, toggle rate, Enable bit if ppm!=0 */
  2097. if (rc == 0) {
  2098. rc = mxc_pm_dither_pll_setup(USBPLL,
  2099. &ap_usb_pll_mfn_values);
  2100. }
  2101. }
  2102.  
  2103. /* Releasing lock */
  2104. spin_unlock_irqrestore(&dvfs_lock, flags);
  2105.  
  2106. return rc;
  2107. }
  2108.  
  2109.  
  2110. /*!
  2111. * Dithering report: return dithering information for all AP PLLs
  2112. * The dithering information includes the PPM and MFN+- values for
  2113. * HFS and LFS.
  2114. * SCM-A11: only AP core normal and AP USB PLLs are used.
  2115. * The information for AP core turbo is just zeroed.
  2116. *
  2117. * @param pllvals ptr to dithering info for all AP PLLs
  2118. */
  2119. void mxc_pm_dither_report(ap_all_plls_mfn_values_t *pllvals)
  2120. {
  2121. unsigned long flags;
  2122. dvfs_op_point_index_t dvfs_op_index;
  2123.  
  2124. /* Acquiring Lock */
  2125. spin_lock_irqsave(&dvfs_lock, flags);
  2126.  
  2127. /*
  2128. * Copy the values from the local structs to the one provided by
  2129. * the caller.
  2130. * SCM-A11 doesn't use the turbo mode values, so just return
  2131. * zeroes.
  2132. */
  2133. for (dvfs_op_index=INDX_FIRST; dvfs_op_index<NUM_DVFSOP_INDEXES; dvfs_op_index++)
  2134. {
  2135. pllvals->ap_core_normal_pll[dvfs_op_index] = opinfo[dvfs_op_index];
  2136. }
  2137. memset(&pllvals->ap_core_turbo_pll, 0, sizeof(pllvals->ap_core_turbo_pll));
  2138. pllvals->ap_usb_pll = ap_usb_pll_mfn_values;
  2139.  
  2140. /* Releasing lock */
  2141. spin_unlock_irqrestore(&dvfs_lock, flags);
  2142. }
  2143. #endif /* CONFIG_MOT_FEAT_PM */
  2144.  
  2145.  
  2146. /*!
  2147. * This function is used to load the module.
  2148. *
  2149. * @return Returns an Integer on success
  2150. */
  2151. static int __init mxc_pm_init_module(void)
  2152. {
  2153. #ifdef CONFIG_MOT_FEAT_PM
  2154. unsigned long adcr;
  2155. int bootloader_used_lfs = 0;
  2156. #endif
  2157.  
  2158. #ifndef CONFIG_MOT_FEAT_PM
  2159. /*
  2160. * If HFSM bit in the PLL Control register is 1
  2161. * but VSTAT bit is high indicating a Low voltage
  2162. * then HFSM and lvs signal should be synchronised
  2163. */
  2164. if (((__raw_readl(PLL0_DP_CTL) & MXC_PLL_DP_CTL_HFSM) != 0) &&
  2165. (mxc_pm_chkvoltage() == LO_VOLT)) {
  2166. mxc_pm_hfsm_sync();
  2167. }
  2168. #endif
  2169.  
  2170. #ifdef CONFIG_MOT_FEAT_PM
  2171. if (mxc_pm_ddram_detected()) {
  2172. printk("mxc_pm_init: memory is DDRAM: DVFS is not allowed\n");
  2173. } else {
  2174. /*** ONLY IF THE MEMORY IS NOT A DDRAM ***/
  2175. printk("mxc_pm_init: memory is not DDRAM: DVFS is allowed\n");
  2176.  
  2177. /* Change the PLL mode to go to HFS mode using the PLL relock with CLK_ON method */
  2178. /* Configure PLL for 399 MHz in HFS mode at low voltage */
  2179.  
  2180. if ((__raw_readl(pll_dp_ctlreg[MCUPLL]) & DP_HFSM) == 0) {
  2181. /*
  2182. * This is the old bootloader. We know that
  2183. * it's booting at 399. Set up for that.
  2184. * PLL0 is at 399 MHz in LFS mode and the core
  2185. * is at low voltage.
  2186. */
  2187. bootloader_used_lfs = 1;
  2188.  
  2189. /* Load the 399Mhz frequency values into the HFS registers. */
  2190. __raw_writel(opinfo[INDX_399].ap_pll_dp_hfs_op, pll_dp_hfs_opreg[MCUPLL]);
  2191. __raw_writel(opinfo[INDX_399].ap_pll_dp_hfs_mfd, pll_dp_hfs_mfdreg[MCUPLL]);
  2192. __raw_writel(opinfo[INDX_399].ap_pll_dp_hfs_mfn, pll_dp_hfs_mfnreg[MCUPLL]);
  2193.  
  2194. /* PLL relock using Pat_ref_clk during relock to switch to HFS mode */
  2195. adcr = (((__raw_readl(MXC_CRMAP_ADCR) | MXC_CRMAP_ADCR_DIV_BYP) | MXC_CRMAP_ADCR_CLK_ON) &
  2196. ~MXC_CRMAP_ADCR_ALT_PLL) & ~MXC_CRMAP_ADCR_DFS_DIVEN;
  2197. __raw_writel(adcr, MXC_CRMAP_ADCR);
  2198.  
  2199. /* Now, raise the core voltage */
  2200. mxc_pm_chgvoltage(HI_VOLT);
  2201.  
  2202. /* Wait until PLL relocks */
  2203. while((__raw_readl(pll_dp_ctlreg[MCUPLL]) & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
  2204.  
  2205. /*
  2206. * PLL0 is at 399 MHz in HFS mode, core is at high voltage
  2207. * Voltage should now be lowered
  2208. */
  2209. /* Select ALT_PLL method */
  2210. adcr = ((__raw_readl(MXC_CRMAP_ADCR) | MXC_CRMAP_ADCR_ALT_PLL) & (~MXC_CRMAP_ADCR_DFS_DIVEN)) &
  2211. (~MXC_CRMAP_ADCR_CLK_ON);
  2212. __raw_writel(adcr, MXC_CRMAP_ADCR);
  2213. /* Now, lower the core voltage */
  2214. mxc_pm_chgvoltage(LO_VOLT);
  2215.  
  2216. cur_dvfs_op_point_index = INDX_399;
  2217.  
  2218. /*
  2219. * PLL0 is at 399 MHz in HFS mode, core is at low voltage
  2220. */
  2221. }
  2222. }
  2223.  
  2224. /*
  2225. * If the bootloader is an older one that uses LFS mode, then
  2226. * we have already set cur_dvfs_op_point_index. Otherwise, we
  2227. * need to do it here.
  2228. */
  2229. if (bootloader_used_lfs == 0) {
  2230. switch (mot_boot_frequency()) {
  2231. case BOOT_FREQUENCY_532:
  2232. cur_dvfs_op_point_index = INDX_532;
  2233. break;
  2234. case BOOT_FREQUENCY_399:
  2235. default:
  2236. cur_dvfs_op_point_index = INDX_399;
  2237. break;
  2238. }
  2239. }
  2240.  
  2241. /*
  2242. * We never use integer scaling since we always use PLL
  2243. * scaling with the ALT_PLL method so we disable
  2244. * integer scaling once here and leave it off.
  2245. */
  2246. mxc_pm_config_scale(DFS_DISABLE);
  2247.  
  2248. /*
  2249. * Normally during PLL relock DVFS, the system transitions to run
  2250. * the ARM core off of ckin (26 MHz), making AHB 13Mhz and IP
  2251. * 6.5 Mhz. This IP clock is too slow.
  2252. * To preserve 13 MHz on pat_ref, we run the ARM core off of
  2253. * ckihX2.
  2254. */
  2255. if (MXC91231_PASS_2_OR_GREATER()) {
  2256. /*
  2257. * Set ASCSR:AP_ISEL to get ckih_x2_ck
  2258. * Set ACSR:ADS to select the clock doubler path. Note that the
  2259. * ADS bit was introduced in Pass 2 silicon.
  2260. */
  2261. #ifdef CONFIG_MACH_MXC27530EVB
  2262. __raw_writel(__raw_readl(MXC_CRMAP_ASCSR) | (long)
  2263. MXC_CRMAP_ASCSR_APISEL, MXC_CRMAP_ASCSR);
  2264. #endif
  2265. __raw_writel(__raw_readl(MXC_CRMAP_ACSR) | (long)
  2266. MXC_CRMAP_ACSR_ADS_PASS2, MXC_CRMAP_ACSR);
  2267. }
  2268. #else /* CONFIG_MOT_FEAT_PM */
  2269.  
  2270. #ifdef CONFIG_MACH_MXC27530EVB
  2271. /*
  2272. * Normally during PLL relock DVFS, the system transitions to run
  2273. * the ARM core off of ckin (26 MHz), making AHB 13Mhz and IP
  2274. * 6.5 Mhz. This IP clock is too slow.
  2275. * To preserve 13 MHz on pat_ref, we run the ARM core off of
  2276. * ckihX2.
  2277. */
  2278. if (MXC91231_PASS_2_OR_GREATER()) {
  2279. /*
  2280. * Set ASCSR:AP_ISEL to get ckih_x2_ck
  2281. * Set ACSR:ADS to select the clock doubler path. Note that the
  2282. * ADS bit was introduced in Pass 2 silicon.
  2283. */
  2284. __raw_writel(__raw_readl(MXC_CRMAP_ASCSR) | (long)
  2285. MXC_CRMAP_ASCSR_APISEL, MXC_CRMAP_ASCSR);
  2286. __raw_writel(__raw_readl(MXC_CRMAP_ACSR) | (long)
  2287. MXC_CRMAP_ACSR_ADS_PASS2, MXC_CRMAP_ACSR);
  2288. }
  2289. #endif
  2290.  
  2291. #endif
  2292.  
  2293. /* Bypass all acknowledgements except MAX */
  2294. __raw_writel((__raw_readl(MXC_CRMAP_AMCR) | AMCR_ACK_BYP),
  2295. MXC_CRMAP_AMCR);
  2296.  
  2297. printk("Low-Level PM Driver module loaded\n");
  2298. return 0;
  2299. }
  2300.  
  2301. /*!
  2302. * This function is used to unload the module
  2303. */
  2304. static void __exit mxc_pm_cleanup_module(void)
  2305. {
  2306. printk("Low-Level PM Driver module Unloaded\n");
  2307. }
  2308.  
  2309. module_init(mxc_pm_init_module);
  2310. module_exit(mxc_pm_cleanup_module);
  2311.  
  2312. EXPORT_SYMBOL(mxc_pm_dvfs);
  2313. EXPORT_SYMBOL(mxc_pm_clockgate);
  2314. EXPORT_SYMBOL(mxc_pm_lowpower);
  2315. EXPORT_SYMBOL(mxc_pm_lp_ack_enable);
  2316. EXPORT_SYMBOL(mxc_pm_lp_ack_disable);
  2317. EXPORT_SYMBOL(mxc_pm_pllscale);
  2318. EXPORT_SYMBOL(mxc_pm_intscale);
  2319.  
  2320. #ifdef CONFIG_MOT_FEAT_PM
  2321. /* De-sense */
  2322. EXPORT_SYMBOL(mxc_pm_dither_control);
  2323. EXPORT_SYMBOL(mxc_pm_dither_setup);
  2324. EXPORT_SYMBOL(mxc_pm_dither_report);
  2325. #endif /* CONFIG_MOT_FEAT_PM */
  2326.  
  2327. MODULE_AUTHOR("Freescale Semiconductor, Inc.");
  2328. MODULE_DESCRIPTION("MXC91231 Low-level PM Driver");
  2329. MODULE_LICENSE("GPL");
  2330.  
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