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  1. // DualClockDivider.sv
  2.  
  3. module DualClockDivider(
  4.     input wire iReset,
  5.     input wire iClock,
  6.     output bit oClockA,
  7.     output bit oClockB);
  8.    
  9.     parameter CLOCK_OUT_A = 64'd15;
  10.     parameter CLOCK_OUT_B = 64'd1;
  11.     parameter CLOCK_INPUT = 64'd100000000;
  12.    
  13.     parameter CLOCK_DIV_A = CLOCK_INPUT / (CLOCK_OUT_A*64'd2);
  14.     parameter CLOCK_DIV_B = CLOCK_INPUT / (CLOCK_OUT_B*64'd2);
  15.        
  16.     bit [63:0] mTimeoutA = CLOCK_DIV_A;
  17.     bit [63:0] mTimeoutB = CLOCK_DIV_B;
  18.     bit mStateA = '0;
  19.     bit mStateB = '0;
  20.    
  21.     assign oClockA = mStateA;
  22.     assign oClockB = mStateB;
  23.        
  24.     always @(posedge iClock, posedge iReset)
  25.     begin
  26.         if (iReset) begin
  27.             mTimeoutA <= CLOCK_DIV_A;
  28.             mTimeoutB <= CLOCK_DIV_B;                
  29.         end
  30.         else begin          
  31.             if (!mTimeoutA) begin
  32.                 mStateA <= ~mStateA;
  33.                 mTimeoutA <= CLOCK_DIV_A;
  34.             end
  35.             else begin
  36.                 --mTimeoutA;
  37.             end                                  
  38.            
  39.             if (!mTimeoutB) begin
  40.                 mStateB <= ~mStateB;
  41.                 mTimeoutB <= CLOCK_DIV_B;
  42.             end
  43.             else begin
  44.                 --mTimeoutB;
  45.             end                                  
  46.         end
  47.     end
  48.        
  49. endmodule
  50.  
  51. // BlinkyTest.sv
  52. `timescale 1ns / 1ps
  53.  
  54. module BlinkyTest(wClockA, wClockB);
  55.     bit rClock = '0;
  56.     bit rReset = '0;
  57.    
  58.     output wire wClockA;
  59.     output wire wClockB;
  60.  
  61.     DualClockDivider mDCD(
  62.         .iClock(rClock),
  63.         .iReset(rReset),
  64.         .oClockA(wClockA),
  65.         .oClockB(wClockB));
  66.    
  67.     initial begin
  68.     #5
  69.         rReset <= '1;
  70.         rClock <= '1;
  71.     #5
  72.         rReset <= '0;
  73.         forever begin
  74.             rClock <= ~rClock;
  75.             #5;
  76.         end    
  77.     end  
  78.    
  79. endmodule
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