// DualClockDivider.sv

module DualClockDivider(
    input wire iReset,
    input wire iClock,
    output bit oClockA,
    output bit oClockB);

    parameter CLOCK_OUT_A = 64'd15;
    parameter CLOCK_OUT_B = 64'd1;
    parameter CLOCK_INPUT = 64'd100000000;

    parameter CLOCK_DIV_A = CLOCK_INPUT / (CLOCK_OUT_A*64'd2);
    parameter CLOCK_DIV_B = CLOCK_INPUT / (CLOCK_OUT_B*64'd2);

    bit [63:0] mTimeoutA = CLOCK_DIV_A;
    bit [63:0] mTimeoutB = CLOCK_DIV_B;
    bit mStateA = '0;
    bit mStateB = '0;

    assign oClockA = mStateA;
    assign oClockB = mStateB;

    always @(posedge iClock, posedge iReset)
    begin
        if (iReset) begin
            mTimeoutA <= CLOCK_DIV_A;
            mTimeoutB <= CLOCK_DIV_B;
        end
        else begin
            if (!mTimeoutA) begin
                mStateA <= ~mStateA;
                mTimeoutA <= CLOCK_DIV_A;
            end
            else begin
                --mTimeoutA;
            end

            if (!mTimeoutB) begin
                mStateB <= ~mStateB;
                mTimeoutB <= CLOCK_DIV_B;
            end
            else begin
                --mTimeoutB;
            end
        end
    end

endmodule

// BlinkyTest.sv
`timescale 1ns / 1ps

module BlinkyTest(wClockA, wClockB);
    bit rClock = '0;
    bit rReset = '0;

    output wire wClockA;
    output wire wClockB;

    DualClockDivider mDCD(
        .iClock(rClock),
        .iReset(rReset),
        .oClockA(wClockA),
        .oClockB(wClockB));

    initial begin
    #5
        rReset <= '1;
        rClock <= '1;
    #5
        rReset <= '0;
        forever begin
            rClock <= ~rClock;
            #5;
        end
    end

endmodule