/* [OvO]wl, FPGA hello world */

module top (
//      inout  BTN1,
//      inout  BTN2,
//      inout  BTN3,
//      inout  BTN4,
        input  clk,
        output LD1,
        output LD2,
        output LD3,
        output LD4,
);

   reg [3:0] LEDS=0;
   reg [3:0] Data=15;
   reg [17:0] Timer=0;

   always @(posedge clk)
     begin
    if( !Timer ) begin
       Data=Data-1;
       LEDS<=Data;
    end;
    Timer=Timer+1;
     end

   assign {LD1, LD2, LD3, LD4} = LEDS;
endmodule