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  1. \documentclass[a4paper, 11pt, oneside]{article}
  2. \usepackage{amssymb}
  3. \usepackage[fleqn]{amsmath}
  4. \usepackage[font=small,labelfont=bf]{caption}
  5. \usepackage{graphicx}
  6. \usepackage{float}
  7. \restylefloat{table}
  8. \usepackage{fullpage}
  9. \usepackage{epstopdf}
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  11. \usepackage{fancyhdr}
  12. \usepackage{listings}
  13. \renewcommand{\headheight}{0.6in}
  14. \setlength{\headwidth}{\textwidth}
  15. \pagestyle{fancy}
  16. \usepackage{siunitx,array,textgreek,booktabs}
  17. \usepackage{gensymb}
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  19. \usepackage{tikz}
  20. \usetikzlibrary{arrows,automata}
  21. \renewcommand{\headheight}{0.6in}
  22. \setlength{\headwidth}{\textwidth}
  23. \fancyhead[R]{ ECS615U  Lab 6 Report}
  24.  
  25.  
  26. \newenvironment{centermath}
  27.  {\begin{center}$\displaystyle}
  28.  {$\end{center}}
  29.  
  30. \begin{document}
  31.  
  32. \title{ECS615U Digital Systems Design Lab 6}
  33. \author{Marco Datola 140803729\\Vojislav Djurovic 140263956\\Jack Cockinis 160980703}
  34. \date{\today}
  35. \maketitle
  36.  
  37. \tableofcontents
  38.  
  39. \section{Introduction}
  40. The aim of this lab was to merge all the different devices implemented in Labs 1-5 to build a microprogram-controlled datapath. Three different microprograms will be implemented, in order to solve the three tasks presented on the lab sheet. The development tools involved in the task were VHDL language, ISim and a FPGA board on which to load our design.
  41. \section{Method}
  42. \begin{enumerate}
  43. \item Determine state diagram from specifications
  44. \item Label states based on 5 possible transitions (CA, CC, BA, BC, CBC)
  45. \item Determine State Transition Table
  46. \item Determine operations to be performed on data for each state
  47. \item Define control words for each state to perform the desired operations on data
  48. \item Define a control ROM which outputs the control word for a given state
  49. \item VHDL source code written for each required module
  50. \item Test bench file written for each module
  51. \item Simulation of the test benches using iSIm
  52. \item Screenshot result
  53. \item Recording and verifying that the simulation matches the expected results
  54. \item Combining the low-level modules to for the microcontroller
  55. \item Test bench file written for the 3 design tasks
  56. \item Simulation of the test benches using iSIm for the 3 design tasks
  57. \item Screenshot results for the 3 design tasks
  58. \item Recording and verifying that the simulation matches the expected results for the 3 design tasks
  59. \item Define constraint files created with PlanAhead for each task
  60. \item Constraint files and source code files programmed to the FPGA board with IMPACT to physically run the code.
  61. \end{enumerate}
  62. \section{Theoretical and experimental results}
  63. In the following sections Truth tables and timing diagrams for all the devices involved in the design are presented. We will exclude from the report those lower-level devices developed in previous labs and those for which the code was provided.
  64.  
  65. \subsection{Function Decode Logic}
  66. From the previous labs, all the low-level modules (except one) required to implement both Control and Data Path are available. The only module we had to implement was the Function Decode Logic.
  67.  
  68. \underline{Truth Table}
  69. \begin{figure}[H]
  70. \begin{center}
  71. \minipage{\textwidth}
  72. \includegraphics[width=0.8\linewidth]{func_dec_logic_truth_table.PNG}
  73. \endminipage\hfill
  74. \end{center}
  75. \end{figure}
  76.  
  77. \underline{Timing Diagram analysis}
  78. The timing diagram visible below confirms what expected from the truth table. A time delay, equivalent to the delay generated by the gate is visible at the beginning of the diagram. This delay then propagates throughout the duration of the Test Bench.
  79. \begin{figure}[H]
  80. \begin{center}
  81. \minipage{1.25\textwidth}
  82. \includegraphics[width=0.9\linewidth]{func_dec_logic.PNG}
  83. \caption{Function Decode Logic timing diagram tested on iSim}
  84. \endminipage\hfill
  85. \end{center}
  86. \end{figure}
  87.  
  88. \subsection{One Counter}
  89. \underline{State Diagram}
  90. The numerical states presented in the below diagram have the following logical meaning
  91. \begin{table}[H]
  92. \centering
  93. \begin{tabular}{ll}
  94. $S_0$ & Start                                               \\
  95. $S_1$ & data = input                                        \\
  96. $S_2$ & ones\_count =0                                      \\
  97. $S_3$ & mask =1                                             \\
  98. $S_4$ & temp = data AND mask                                \\
  99. $S_5$ & ones\_count = ones\_count + temp                    \\
  100. $S_6$ & data = data \textgreater\textgreater1 (shift right) \\
  101. $S_7$ & Output = ones\_count                              
  102. \end{tabular}
  103. \end{table}
  104. \begin{center}
  105. \begin{tikzpicture}[>=stealth',shorten >=1pt,auto,node distance=2cm]
  106.   \node[initial,state,accepting] (S0)      {$S_0$};
  107.   \node[state]         (S1) [below of=S0]  {$S_1$};
  108.   \node[state]         (S2) [below of=S1] {$S_2$};
  109.   \node[state]         (S3) [below of=S2] {$S_3$};
  110.   \node[state]         (S4) [below of=S3] {$S_4$};
  111.   \node[state]         (S5) [below of=S4] {$S_5$};
  112.   \node[state]         (S6) [below of=S5] {$S_6$};
  113.   \node[state]         (S7) [below of=S6] {$S_7$};
  114.  
  115.  
  116.  
  117.   \path[->] (S0)  edge [loop above] node {Start=0} (S0);
  118.   \path[->] (S0)  edge  node {Start=1} (S1);
  119.   \path[->] (S1)  edge  node {} (S2);
  120.   \path[->] (S2)  edge  node {} (S3);
  121.   \path[->] (S3)  edge  node {} (S4);
  122.   \path[->] (S4)  edge  node {} (S5);
  123.   \path[->] (S5)  edge  node {} (S6);
  124.   \path[->] (S6)  edge  [bend left] node {data!=0} (S4);
  125.   \path[->] (S6)  edge  node {data=0} (S7);
  126.   \path[->] (S7)  edge  [bend left] node {Done=1} (S0);
  127.              
  128. \end{tikzpicture}
  129. \end{center}
  130.  
  131.  
  132. \underline{State Labelling Table}
  133. A table of the transition labels assigned to each state is presented below.
  134. \begin{figure}[H]
  135. \begin{center}
  136. \minipage{\textwidth}
  137. \includegraphics[width=0.8\linewidth]{ones_trans_label.PNG}
  138. \endminipage\hfill
  139. \end{center}
  140. \end{figure}
  141.  
  142. \underline{State Transition Table & Control words}
  143. A table of the transition labels assigned to each state is presented below. In this the control words associated with the particular state are presented.
  144. \begin{figure}[H]
  145. \begin{center}
  146. \minipage{\textwidth}
  147. \includegraphics[width=\linewidth]{ones_trans_table.PNG}
  148. \endminipage\hfill
  149. \end{center}
  150. \end{figure}
  151. \underline{Timing Diagram analysis}
  152. The timing diagram visible below displays the operation of control and data paths. It confirms what expected from the transition table, hence confirms the correctness of the design. A time delay, equivalent to the delay generated by the gate is visible at the beginning of the diagram. This delay then propagates throughout the duration of the Test Bench.
  153. \begin{figure}[H]
  154. \begin{center}
  155. \minipage{1.25\textwidth}
  156. \includegraphics[width=0.9\linewidth]{Lab6_Task1.PNG}
  157. \caption{Ones Counter timing diagram tested on iSim}
  158. \endminipage\hfill
  159. \end{center}
  160. \end{figure}
  161.  
  162. \subsection{Ones Bouncing}
  163. \underline{State Diagram}
  164. The numerical states presented in the below diagram have the following logical meaning
  165. \begin{table}[H]
  166. \centering
  167. \begin{tabular}{ll}
  168. $S_0$ & Loop until start = 1, CC to S$_1$                      \\
  169. $S_1$ & Inputs $data$ and checks $data\neq 0$, branch to $S_3$      \\
  170. $S_2$ & Branch to $S_0 $                                       \\
  171. $S_3$ & Forces 0 to $Sum$                                     \\
  172. $S_4$ & Increment $Sum$                                      \\
  173. $S_5$ & Rotate $Sum$ left                    \\
  174. $S_6$ & Rotate $Sum$ left \\
  175. $S_7$ & Rotate $Sum$ left                               \\
  176. $S_8$ & Rotate $Sum$ right                   \\
  177. $S_9$ & Rotate $Sum$ right                    \\
  178. $S_{10}$ & Decrement $data$, check $data \neq 0$, Branch to $S_3$            \\
  179. $S_{11}$ & $Data = 0$, Branch to $S_0$
  180.  
  181. \end{tabular}
  182. \end{table}
  183. \begin{center}
  184. \begin{tikzpicture}[>=stealth',shorten >=1pt,auto,node distance=2cm]
  185.   \node[initial,state,accepting] (S0)      {$S_0$};
  186.   \node[state]         (S1) [below of=S0]  {$S_1$};
  187.   \node[state]         (S2) [left of=S1] {$S_2$};
  188.   \node[state]         (S3) [below of=S1] {$S_3$};
  189.   \node[state]         (S4) [below of=S3] {$S_4$};
  190.   \node[state]         (S5) [below of=S4] {$S_5$};
  191.   \node[state]         (S6) [below of=S5] {$S_6$};
  192.   \node[state]         (S7) [below of=S6] {$S_7$};
  193.   \node[state]         (S8) [below of=S7] {$S_8$};
  194.   \node[state]         (S9) [below of=S8] {$S_9$};
  195.   \node[state]         (S10) [below of=S9] {$S_{10}$};
  196.   \node[state]         (S11) [below of=S10] {$S_{11}$};
  197.  
  198.  
  199.   \path[->] (S0)  edge [loop above] node {Start=0} (S0);
  200.   \path[->] (S0)  edge  node {Start=1} (S1);
  201.   \path[->] (S1)  edge  node {data = 0} (S2);
  202.   \path[->] (S1)  edge  node {data != 0} (S3);
  203.   \path[->] (S2)  edge  node {} (S0);
  204.   \path[->] (S3)  edge  node {} (S4);
  205.   \path[->] (S4)  edge  node {} (S5);
  206.   \path[->] (S5)  edge  node {} (S6);
  207.   \path[->] (S6)  edge  node {} (S7);
  208.   \path[->] (S7)  edge  node {} (S8);
  209.   \path[->] (S8)  edge  node {} (S9);
  210.   \path[->] (S9)  edge  node {} (S10);
  211.   \path[->] (S10)  edge  node {} (S11);
  212.   \path[->] (S10)  edge  [bend left] node {data != 0} (S3);
  213.   \path[->] (S11)  edge  [bend right] node {done =1} (S0);
  214.              
  215. \end{tikzpicture}
  216. \end{center}
  217.  
  218. \underline{State Labelling Table}
  219. A table of the transition labels assigned to each state is presented below.
  220. \begin{figure}[H]
  221. \begin{center}
  222. \minipage{\textwidth}
  223. \includegraphics[width=0.8\linewidth]{ob_trans_label.PNG}
  224. \endminipage\hfill
  225. \end{center}
  226. \end{figure}
  227.  
  228. \underline{State Transition Table & Control words}
  229. A table of the transition labels assigned to each state is presented below. In this the control words associated with the particular state are presented.
  230. \begin{figure}[H]
  231. \begin{center}
  232. \minipage{\textwidth}
  233. \includegraphics[width=\linewidth]{ob_trans_table.PNG}
  234. \endminipage\hfill
  235. \end{center}
  236. \end{figure}
  237. \underline{Timing Diagram analysis}
  238. The timing diagram visible below displays the operation of control and data paths. In this case $data = 4_{10} = 0100_{B}$ is inputted in the system. This causes the bouncing to occur four times. It confirms what expected from the transition table, hence confirms the correctness of the design. In particular, at the end of each loop for a whole clock period high impedance is visible at the output. A time delay, equivalent to the delay generated by the gates is visible at the beginning of the diagram. This delay then propagates throughout the duration of the Test Bench.
  239. \begin{figure}[H]
  240. \begin{center}
  241. \minipage{1.25\textwidth}
  242. \includegraphics[width=0.9\linewidth]{lab6_task2_A.PNG}
  243. \caption{Ones Bouncing timing diagram tested on iSim}
  244. \endminipage\hfill
  245. \end{center}
  246. \end{figure}
  247. In this case $data = 0$ is inputted in the system. Here we see no bouncing occurs.
  248. \begin{figure}[H]
  249. \begin{center}
  250. \minipage{1.25\textwidth}
  251. \includegraphics[width=0.9\linewidth]{lab6_task2_B.PNG}
  252. \caption{Ones Bouncing timing diagram tested on iSim}
  253. \endminipage\hfill
  254. \end{center}
  255. \end{figure}
  256.  
  257. \subsection{Alt Bouncing}
  258. \underline{State Diagram}
  259. The numerical states presented in the below diagram have the following logical meaning
  260. \begin{table}[H]
  261. \centering
  262. \begin{tabular}{ll}
  263. $S_0$ & Loop until start = 1, CC to S$_1$                      \\
  264. $S_1$ & Inputs $data$ and checks $data\neq 0$, branch to $S_3$      \\
  265. $S_2$ & Branch to $S_0 $                                       \\
  266. $S_3$ & Takes in $ALT$, branches to $S_{10}$ \\
  267. $S_4$ & Forces 0 into $Sum$                                     \\
  268. $S_5$ & Allows to print initial sum \\
  269. $S_6$ & Shift $Sum$ left with $input =1$ \\
  270. $S_7$ &Complement $Sum$, check $¬sum \neq 0$, branch $S_6$ \\
  271. $S_8$ & Decrement $input$, checks $input \neq 0$, branch $S_4$\\
  272. $S_9$ & Allows $output$, branches $S_0$ \\
  273. $S_{10}$ & Forces 0 into $Sum$ \\
  274. $S_{11}$ & Complement $Sum$ \\
  275. $S_{12}$ & Shift $Sum$ left with $input =0$, if $Sum \neq 0$ branch $S_{12}$\\
  276. $S_{13}$ & Decrement $input$, check $input \neq 0$, branch $S_{11}$\\
  277. $S_{14}$ & Allows $ouput$, branches to $S_0$
  278. \end{tabular}
  279.  
  280. \end{table}
  281. \begin{center}
  282. \begin{tikzpicture}[>=stealth',shorten >=1pt,auto,node distance=2.5cm]
  283.   \node[initial,state,accepting] (S0)      {$S_0$};
  284.   \node[state]         (S1) [below of=S0]  {$S_1$};
  285.   \node[state]         (S2) [right of=S1] {$S_2$};
  286.   \node[state]         (S3) [below of=S1] {$S_3$};
  287.   \node[state]         (S4) [left of=S3] {$S_4$};
  288.   \node[state]         (S5) [below of=S4] {$S_5$};
  289.   \node[state]         (S6) [below of=S5] {$S_6$};
  290.   \node[state]         (S7) [below of=S6] {$S_7$};
  291.   \node[state]         (S8) [below of=S7] {$S_8$};
  292.   \node[state]         (S9) [below of=S8] {$S_9$};
  293.   \node[state]         (S10) [right of=S3] {$S_{10}$};
  294.   \node[state]         (S11) [below of=S10] {$S_{11}$};
  295.   \node[state]         (S12) [below of=S11] {$S_{12}$};
  296.   \node[state]         (S13) [below of=S12] {$S_{13}$};
  297.   \node[state]         (S14) [below of=S13] {$S_{14}$};
  298.  
  299.  
  300.   \path[->] (S0)  edge [loop above] node {Start=0} (S0);
  301.   \path[->] (S0)  edge  node {Start=1} (S1);
  302.   \path[->] (S1)  edge  node {data = 0} (S2);
  303.   \path[->] (S1)  edge  node {data != 0} (S3);
  304.   \path[->] (S2)  edge  node [bend right]{} (S0);
  305.   \path[->] (S3)  edge  node {Alt = 0} (S4);
  306.   \path[->] (S3)  edge  node {Alt =1 } (S10);
  307.   \path[->] (S4)  edge  node {} (S5);
  308.   \path[->] (S5)  edge  node {} (S6);
  309.   \path[->] (S6)  edge  node {} (S7);
  310.   \path[->] (S7)  edge  node {data = 0} (S8);
  311.   \path[->] (S7)  edge  [bend right] node {data != 0} (S6);
  312.   \path[->] (S8)  edge  node {data =0} (S9);
  313.   \path[->] (S8)  edge  [bend left] node {data !=0} (S4);
  314.   \path[->] (S9)  edge  [bend left=70] node {done =1} (S0);
  315.   \path[->] (S10)  edge  node {} (S11);
  316.   \path[->] (S11)  edge  node {} (S12);
  317.   \path[->] (S12)  edge  [loop right] node {data != 0} (S12);
  318.   \path[->] (S12)  edge  node {data = 0} (S13);
  319.   \path[->] (S13)  edge  node {data =0} (S14);
  320.   \path[->] (S13)  edge  [bend left] node {data !=0} (S11);
  321.   \path[->] (S14)  edge  [bend right=90] node {done = 1}(S0);
  322.  
  323.              
  324. \end{tikzpicture}
  325. \end{center}
  326.  
  327. \underline{State Labelling Table}
  328. A table of the transition labels assigned to each state is presented below.
  329. \begin{figure}[H]
  330. \begin{center}
  331. \minipage{\textwidth}
  332. \includegraphics[width=0.8\linewidth]{ab_trans_label.PNG}
  333. \endminipage\hfill
  334. \end{center}
  335. \end{figure}
  336.  
  337. \underline{State Transition Table & Control words}
  338. A table of the transition labels assigned to each state is presented below. In this the control words associated with the particular state are presented.
  339. \begin{figure}[H]
  340. \begin{center}
  341. \minipage{\textwidth}
  342. \includegraphics[width=0.8\linewidth]{ab_trans_table.PNG}
  343. \endminipage\hfill
  344. \end{center}
  345. \end{figure}
  346. \underline{Timing Diagram analysis}
  347. The timing diagram visible below displays the operation of control and data paths. In this case $data = 3_{10} = 0011_{B}$ and $ALT = 1$ are inputted in the system. These conditions impose the data to bounce 3 times, starting at 1111. The diagram confirms what expected from the transition table, hence confirms the correctness of the design. In particular, at the end of each loop for a whole clock period high impedance is visible at the output. A time delay, equivalent to the delay generated by the gate is visible at the beginning of the diagram. This delay then propagates throughout the duration of the Test Bench.
  348.  
  349. \begin{figure}[H]
  350. \begin{center}
  351. \minipage{1.25\textwidth}
  352. \includegraphics[width=0.9\linewidth]{Task3_Alt1.PNG}
  353. \caption{Alt Bouncing timing diagram tested on iSim}
  354. \endminipage\hfill
  355. \end{center}
  356. \end{figure}
  357. In this case $data = 3_{10} = 0011_{B}$ and $ALT = 0$ are inputted in the system. These conditions impose the data to bounce 3 times, starting at 0000. High impedance is observed after every output because the looping mechanism has to go through an addition state ($S_7$ Branch Condition $S_7$) in order for the desired result to be generated correctly.
  358. \begin{figure}[H]
  359. \begin{center}
  360. \minipage{1.25\textwidth}
  361. \includegraphics[width=0.9\linewidth]{Task3_Alt0.PNG}
  362. \caption{Alt Bouncing timing diagram tested on iSim}
  363. \endminipage\hfill
  364. \end{center}
  365. \end{figure}
  366.  
  367. \section{Discussion}
  368. As tested in the lab, the results observed on the FPGA are in agreement both with the Timing Diagram and with the Truth table of the tested device. We assume there's going to be a different time delay in the FPGA due to non-idealised conditions. As mentioned in the Timing Diagram analysis for every component, this non-idealised conditions are modelled by generating a small delay at the beginning of the output signal.
  369.  
  370. \section{Conclusion}
  371.  
  372. In this lab we were able to successfully write, simulate and test all the required devices and microprograms.
  373. All the simulation results matched the theoretical expectations which confirms every level of our design is in correct working order, from lab 1 through to lab 6.
  374. \end{document}
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