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autoinfer carry chains patch

a guest Sep 16th, 2019 100 Never
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  1. From b4994493715c0e12127b6b98bfb4e66843bfbf80 Mon Sep 17 00:00:00 2001
  2. From: Karol Gugala <kgugala@antmicro.com>
  3. Date: Mon, 16 Sep 2019 17:16:28 +0200
  4. Subject: [PATCH] utils: vlog_to_pbtype: autoinfer carry chains on pins
  5.  
  6. Signed-off-by: Karol Gugala <kgugala@antmicro.com>
  7. ---
  8. utils/vlog/vlog_to_pbtype.py | 17 +++++++++++++----
  9.  1 file changed, 13 insertions(+), 4 deletions(-)
  10.  
  11. diff --git a/utils/vlog/vlog_to_pbtype.py b/utils/vlog/vlog_to_pbtype.py
  12. index 236013a1..847b9324 100755
  13. --- a/utils/vlog/vlog_to_pbtype.py
  14. +++ b/utils/vlog/vlog_to_pbtype.py
  15. @@ -451,7 +451,7 @@ def get_list_name_and_length(l: List[str]) -> Tuple[str, int]:
  16.      return list_name, len(l)
  17.  
  18.  
  19. -def make_ports(clocks, mod, pb_type_xml, only_type=None):
  20. +def make_ports(clocks, mod, pb_type_xml, yj, only_type=None):
  21.      for name, width, bits, iodir in mod.ports:
  22.          ioattrs = {"name": name, "num_pins": str(width)}
  23.          pclass = mod.net_attr(name, "PORT_CLASS")
  24. @@ -475,6 +475,15 @@ def make_ports(clocks, mod, pb_type_xml, only_type=None):
  25.          port_attrs = mod.port_attrs(name)
  26.  
  27.          carry_name = port_attrs.get('carry', None)
  28. +        if carry_name is None and width == 1:
  29. +            for con in mod.port_conns(name):
  30. +                for cell, celltype in mod.cells:
  31. +                    cmod = yj.module(celltype)
  32. +                    cellconns = mod.cell_conns(cell, iodir)
  33. +                    for port, net in cellconns:
  34. +                        if net == con:
  35. +                            cport_attrs = cmod.port_attrs(port)
  36. +                            carry_name = cport_attrs.get('carry', None)
  37.          if carry_name:
  38.              ET.SubElement(
  39.                  port_xml, 'pack_pattern', {
  40. @@ -745,9 +754,9 @@ def make_pb_type(
  41.  
  42.      # Create the pins for this pb_type
  43.      clocks = yosys.run.list_clocks(args.infiles, mod.name)
  44. -    make_ports(clocks, mod, pb_type_xml, "clocks")
  45. -    make_ports(clocks, mod, pb_type_xml, "inputs")
  46. -    make_ports(clocks, mod, pb_type_xml, "outputs")
  47. +    make_ports(clocks, mod, pb_type_xml, yj, "clocks")
  48. +    make_ports(clocks, mod, pb_type_xml, yj, "inputs")
  49. +    make_ports(clocks, mod, pb_type_xml, yj, "outputs")
  50.  
  51.      if modes and not mode_processing:
  52.          for mode in modes:
  53. --
  54. 2.23.0
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