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Mar 15th, 2019
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VHDL 2.60 KB | None | 0 0
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity shifter_unit is
  8.    Port (
  9.     B: in STD_LOGIC_VECTOR(15 downto 0);
  10.     FS: in STD_LOGIC_VECTOR(4 downto 0);
  11.     IL, IR : in STD_LOGIC;
  12.     H: out STD_LOGIC_VECTOR(15 downto 0)
  13.    );
  14. end shifter_unit;
  15.  
  16. architecture Behavioral of shifter_unit is
  17.     Component mux_3to1
  18.         Port(
  19.         A, B, C: in STD_LOGIC;
  20.         S : in std_logic_vector(1 downto 0);
  21.         Z: out STD_LOGIC_vector(15 downto 0)
  22.         );
  23.     End Component;
  24.  
  25.  
  26. signal S : std_logic_vector(1 downto 0);
  27.  
  28.  
  29. begin
  30.  
  31. S <= "00" when FS = "10000"else
  32.      "01" when FS = "10100" else
  33.      "10" when FS = "11000" else
  34.      "11" after 1 ns;
  35.        
  36. mux00: mux_3to1 PORT MAP(
  37.     A => B(0),
  38.     B => B(1),
  39.     C => IL,
  40.     S => S,
  41.     Z => H(0)
  42.     );
  43.    
  44. mux01: mux_3to1 PORT MAP(
  45.    A => B(1),
  46.    B => B(2),
  47.    C => B(0),
  48.    S => S,
  49.    Z => H(1)
  50.    );
  51.    
  52. mux02: mux_3to1 PORT MAP(
  53.   A => B(2),
  54.   B => B(3),
  55.   C => B(1),
  56.   S => S,
  57.   Z => H(2)
  58.   );
  59. mux03: mux_3to1 PORT MAP(
  60.    A => B(3),
  61.    B => B(4),
  62.    C => B(2),
  63.    S => S,
  64.    Z => H(3)
  65.    );
  66.    
  67. mux04: mux_3to1 PORT MAP(
  68.     A => B(4),
  69.     B => B(5),
  70.     C => B(3),
  71.     S => S,
  72.     Z => H(4)
  73.     );
  74.    
  75. mux05: mux_3to1 PORT MAP(
  76.     A => B(5),
  77.     B => B(6),
  78.     C => B(4),
  79.     S => S,
  80.     Z => H(5)
  81.     );
  82.    
  83. mux06: mux_3to1 PORT MAP(
  84.     A => B(6),
  85.     B => B(7),
  86.     C => B(5),
  87.     S => S,
  88.     Z => H(6)
  89.     );
  90.    
  91. mux07: mux_3to1 PORT MAP(
  92.     A => B(7),
  93.     B => B(8),
  94.     C => B(6),
  95.     S => S,
  96.     Z => H(7)
  97.     );
  98.    
  99. mux08: mux_3to1 PORT MAP(
  100.     A => B(8),
  101.     B => B(9),
  102.     C => B(7),
  103.     S => S,
  104.     Z => H(8)
  105.     );
  106.    
  107. mux09: mux_3to1 PORT MAP(
  108.     A => B(9),
  109.     B => B(10),
  110.     C => B(8),
  111.     S => S,
  112.     Z => H(9)
  113.     );
  114.        
  115. mux10: mux_3to1 PORT MAP(
  116.     A => B(10),
  117.     B => B(11),
  118.     C => B(9),
  119.     S => S,
  120.     Z => H(10)
  121.     );
  122.        
  123. mux11: mux_3to1 PORT MAP(
  124.     A => B(11),
  125.     B => B(12),
  126.     C => B(10),
  127.     S => S,
  128.     Z => H(11)
  129.     );
  130.        
  131.  mux12: mux_3to1 PORT MAP(
  132.     A => B(12),
  133.     B => B(13),
  134.     C => B(11),
  135.     S => S,
  136.     Z => H(12)
  137.     );
  138.        
  139.  mux13: mux_3to1 PORT MAP(
  140.     A => B(13),
  141.     B => B(14),
  142.     C => B(12),
  143.     S => S,
  144.     Z => H(13)
  145.     );
  146.        
  147. mux14: mux_3to1 PORT MAP(
  148.     A => B(14),
  149.     B => B(15),
  150.     C => B(13),
  151.     S => S,
  152.     Z => H(14)
  153.     );
  154.      
  155. mux15: mux_3to1 PORT MAP(
  156.     A => B(15),
  157.     B => IR,
  158.     C => B(14),
  159.     S => S,
  160.     Z => H(15)
  161.     );
  162.        
  163. end Behavioral;
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