library ieee;
use ieee.std_logic_1164.all;

entity dummy is
    generic (
        LENGTH : natural);
    port (
        A : in std_logic_vector (LENGTH - 1 downto 0); -- #2a
        --A : in std_logic_vector (1 - 1 downto 0); -- #2b
        Q : out std_logic);
end entity;

architecture rtl of dummy is
begin
    Q <= '0';
end architecture;


library ieee;
use ieee.std_logic_1164.all;

entity modelsim_others_bug_testbench is
end modelsim_others_bug_testbench;

architecture rtl of modelsim_others_bug_testbench is
    signal x : std_logic;
begin
    x <= '0';

    dummy_i: entity work.dummy
        generic map (
            LENGTH => 1)
        port map (
            A => (others => x), -- #1a
            --A => (others => '0'), -- #1b
            Q => open);
end architecture;