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-- Company:
-- Engineer:
--
-- Create Date: 04/17/2018 03:53:03 AM
-- Design Name:
-- Module Name: ControlUnit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ControlUnit is
    Port ( instruction : in std_logic_vector(2 downto 0); --opcode
           regWrite : out STD_LOGIC;
           ALUsrc : out STD_LOGIC;
           branch : out STD_LOGIC;
           jump : out STD_LOGIC;
           ALUop : out STD_LOGIC_VECTOR (2 downto 0);
           memWrite : out STD_LOGIC;
           memToReg : out STD_LOGIC;
           extOp : out STD_LOGIC;
           regDst : out STD_LOGIC);
end ControlUnit;

architecture Behavioral of ControlUnit is

begin

process(instruction(2 downto 0))
begin
    --initializare
    regWrite <= '0';
    ALUsrc <= '0';
    branch <= '0';
    jump <= '0';
    ALUop <= "000";
    memWrite <= '0';
    memToReg <= '0';
    extOp <= '0';
    regDst <= '0';

    case instruction(2 downto 0) is
        --r type instruction
        when "000" =>  regWrite <= '1'; ------
                       ALUsrc <= '0';
                       branch <= '0';
                       jump <= '0';
                       ALUop <= "000";
                       memWrite <= '0';
                       memToReg <= '0';
                       extOp <= '0';
                       regDst <= '1'; ---------

        --ADDI
        when "001" =>  regWrite <= '1'; -------
                       ALUsrc <= '1'; --------
                       branch <= '0';
                       jump <= '0';
                       ALUop <= "001";
                       memWrite <= '0';
                       memToReg <= '0';
                       extOp <= '1'; --------
                       regDst <= '0';

        --LOAD WORD
        when "010" =>  regWrite <= '1'; ---------
                       ALUsrc <= '1'; ---------
                       branch <= '0';
                       jump <= '0';
                       ALUop <= "001";
                       memWrite <= '0';
                       memToReg <= '1'; ----------
                       extOp <= '1'; ----------
                       regDst <= '0';

        --STORE WORD
        when "011" =>  regWrite <= '0';
                       ALUsrc <= '1'; ------------
                       branch <= '0';
                       jump <= '0';
                       ALUop <= "001";
                       memWrite <= '1'; ------------
                       memToReg <= '0';
                       extOp <= '1'; ------------
                       regDst <= '0';

        --BEQ
        when "100" =>  regWrite <= '0';
                       ALUsrc <= '0';
                       branch <= '1'; ---------
                       jump <= '0';
                       ALUop <= "010";
                       memWrite <= '0';
                       memToReg <= '0';
                       extOp <= '1'; ----------
                       regDst <= '0';

         --ANDI
         when "101" =>  regWrite <= '1'; ---------
                        ALUsrc <= '1'; --------
                        branch <= '0';
                        jump <= '0';
                        ALUop <= "011";
                        memWrite <= '0';
                        memToReg <= '0';
                        extOp <= '0';
                        regDst <= '0';

         --ORI
         when "110" =>  regWrite <= '1'; ---------
                        ALUsrc <= '1'; --------
                        branch <= '0';
                        jump <= '0';
                        ALUop <= "100";
                        memWrite <= '0';
                        memToReg <= '0';
                        extOp <= '0';
                        regDst <= '0';

          --JUMP
          when "111" =>  regWrite <= '0';
                         ALUsrc <= '0';
                         branch <= '0';
                         jump <= '1'; ---------
                         ALUop <= "000";
                         memWrite <= '0';
                         memToReg <= '0';
                         extOp <= '0';
                         regDst <= '0';
        end case;
end process;
end Behavioral;