library ieee;
use ieee.std_logic_1164.all;
use work.all;
use ieee.numeric_std.all;
use work.all_functions.all;

entity my_gates is
port(
        a, b : in std_logic;
        and_out, or_out, xor_out : out std_logic
);
end my_gates;

architecture gates of my_gates is

    function f_xor(s1, s2 : std_logic) return std_logic is
            begin
                return (s1 xor s2);
    end f_xor;


    procedure p_and_or(signal s1,s2 : std_logic; signal out1_and, out2_or : out std_logic) is
        begin
            out1_and <= s1 and s2;
            out2_or <= s1 or s2;
    end p_and_or;

begin

    process(a, b)
    begin
        xor_out <= f_xor(a,b);
        p_and_or(a,b, and_out, or_out);
    end process;
end gates;