traffic_light.sv

module traffic_light (
    input logic clk,
    input logic rst,
    input logic button,
    output logic red,
    output logic yellow,
    output logic green
);

logic [5:0] t;

enum {S_RED, S_YELLOW_TO_GREEN, S_YELLOW_TO_RED, S_GREEN, S_WAITING} state;

always @(posedge clk) begin
    if (rst)
        state <= S_GREEN;

    else case (state)
    S_GREEN:
        if (button)
            if (t == 60) begin
                state <= S_YELLOW_TO_RED;
                t = 6'h0;
            end
        else
            state <= S_WAITING;

    S_WAITING:
        if (t == 60) begin
                state <= S_YELLOW_TO_RED;
                t = 6'h0;
        end

    S_YELLOW_TO_RED:
        if (t == 3) begin
            state <= S_RED;
            t = 6'h0;
        end

    S_RED:
        if (t == 20) begin
            state <= S_YELLOW_TO_GREEN;
            t = 6'h0;
        end

    S_YELLOW_TO_GREEN:
        if(t == 3) begin
            state <= S_GREEN;
            t = 6'h0;
    end
    endcase
end

always_ff @(posedge clk)
    if (rst)
        t = 6'h0;
    else if(t != 60)
        t <= t + 1;

assign red = (state == S_RED || state == S_YELLOW_TO_GREEN);
assign yellow = (state == S_YELLOW_TO_GREEN || state == S_YELLOW_TO_RED);
assign green = (state == S_GREEN || state == S_WAITING);

endmodule