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-- Company:
-- Engineer:
--
-- Create Date:    11:03:43 01/18/2019
-- Design Name:
-- Module Name:    ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
    Port ( iA : in  STD_LOGIC_VECTOR (15 downto 0);
           iB : in  STD_LOGIC_VECTOR (15 downto 0);
           iSEL : in  STD_LOGIC_VECTOR (3 downto 0);
           oC : out  STD_LOGIC_VECTOR (15 downto 0);
           oSIGN : out  STD_LOGIC;
           oCARRY : out  STD_LOGIC;
           oZERO : out  STD_LOGIC);
end ALU;

architecture Behavioral of ALU is
signal sC : STD_LOGIC_VECTOR (16 downto 0);
signal sA :	STD_LOGIC_VECTOR (16 downto 0);
signal sB :	STD_LOGIC_VECTOR (16 downto 0);
begin
sA <= '0' & iA(15 downto 0);
sB <= '0' & iB(15 downto 0);

sC <= sA when iSEL="0000" else
		sA+sB when iSEL="0001" else
		sA-sB when iSEL="0010" else
		sA and sB when iSEL="0011" else
		sA or sB when iSEL="0100" else
		not(sA) when iSEL="0101" else
		sA + 1 when iSEL="0110" else
		sA - 1 when iSEL="0111" else
		'0' & sA(14 downto 0) & '0'  when iSEL="1000" else
		'0' & '0' & sA(14 downto 0) when iSEL="1001" else
		not(sA) + 1 when iSEL="1010" else
		sA(16 downto 15) & sA(15 downto 1) when iSEL="1011" else
		"00000000000000000";

oZERO <= '1' when sC = "00000000000000000" else '0';
oCARRY <= sC(16);
oSIGN <= sC(15);
oC <= sC(15 downto 0);
end Behavioral;