/******************************************************************************
 *                                                                            *
 * Module:       Peripheral_on_External_Bus                                   *
 * Description:                                                               *
 *      This module is used for the registers for part I of the bus           *
 *   communication exercise in Altera's computer organization lab set.        *
 *                                                                            *
 * This is a skeleton module that must be completed as part of this exercise. *
 *                                                                            *
 *****************************************************************************/

module Peripheral_on_External_Bus (
	// Inputs
	clk_clk,
	reset_reset_n,

	address,
	bus_enable,
	byte_enable,
	rw,
	write_data,

	// Outputs
	acknowledge,
	read_data,

	register_0,
	register_1,
	register_2,
	register_3
);

/*****************************************************************************
 *                             Port Declarations                             *
 *****************************************************************************/

// Inputs
input				clk_clk;
input				reset_reset_n;

input		[19:0]	address;
input					bus_enable;
input		[1:0]		byte_enable;
input					rw;
input		[15:0]	write_data;

// Outputs
output				acknowledge;
output	 	[15:0]	read_data;

output	reg	[15:0]	register_0;
output	reg	[15:0]	register_1;
output	reg	[15:0]	register_2;
output	reg	[15:0]	register_3;

/*****************************************************************************
 *                             Sequential Logic                              *
 *****************************************************************************/

always @(posedge clk_clk)
begin
	if (reset_reset_n == 0)
		begin
			register_0 <= 16'h0000;
			register_1 <= 16'h0000;
			register_2 <= 16'h0000;
			register_3 <= 16'h0000;
		end

	else if (~rw & acknowledge & address[19])
		begin
			case (address[2:1])
				2'b00: register_0 <= write_data;
				2'b01: register_1 <= write_data;
				2'b10: register_2 <= write_data;
				2'b11: register_3 <= write_data;
			endcase
		end

end

/*****************************************************************************
 *                            Combinational Logic                            *
 *****************************************************************************/

assign acknowledge = address[19] ? bus_enable : 1'bz;

assign read_data	 = (address[19] & rw) ?
						  (({16{~address[2] & ~address[1]}} & register_0) +
							({16{~address[2] &  address[1]}} & register_1) +
							({16{ address[2] & ~address[1]}} & register_2) +
							({16{ address[2] &  address[1]}} & register_3)) :
							{16{1'bz}};	// if MSB=0 or rw=0, leave read_data for SRAM




endmodule