process(clk, rst)
    variable shifted : std_logic_vector(15 downto 0) := (others => '0');
    begin
        if(rst = '1') then
            state <= load;
            seed  <= load;
            shifted := (others => '0');
        elsif(rising_edge(clk)) then
            shifted(15 - 1 downto 0) := state(15 downto 0 + 1);
            shifted(15) := '0';
            if(shifted(0) = '1') then
                state <= shifted xor x"B400";
            else
                state <= shifted;
            end if;
        end if;
    end process;