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VHDL 4-Bit Mux Testbench

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Sep 6th, 2018
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  1. --Question #3 (Dean Nguyen)--
  2. LIBRARY IEEE;
  3. USE IEEE.STD_LOGIC_1164.ALL;
  4. USE IEEE.STD_LOGIC_UNSIGNED.ALL;
  5. USE IEEE.NUMERIC_STD.ALL;
  6. ENTITY Four_Bit_Multi_TB IS
  7. END Four_Bit_Multi_TB;
  8.  
  9. ARCHITECTURE behavioral OF Four_Bit_Multi_TB IS
  10. COMPONENT Four_Bit_Multi
  11.     PORT(   a0, a1, a2, a3, b0, b1, b2, b3, sel : IN STD_LOGIC;
  12.             z0, z1, z2, z3                          : OUT STD_LOGIC);
  13. END COMPONENT;
  14. --Inputs--
  15. SIGNAL a_TB : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
  16. SIGNAL b_TB : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
  17. SIGNAL sel_TB : STD_LOGIC := '0';
  18. --Outputs--
  19. SIGNAL z_TB : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
  20. BEGIN
  21.     uut: Four_Bit_Multi PORT MAP (
  22.         a0 => a_TB(0),
  23.         a1 => a_TB(1),
  24.         a2 => a_TB(2),
  25.         a3 => a_TB(3),
  26.         b0 => b_TB(0),
  27.         b1 => b_TB(1),
  28.         b2 => b_TB(2),
  29.         b3 => b_TB(3),
  30.         sel => sel_TB,
  31.         z0 => z_TB(0),
  32.         z1 => z_TB(1),
  33.         z2 => z_TB(2),
  34.         z3 => z_TB(3));
  35.     stimulus : PROCESS
  36.     BEGIN
  37.         FOR i IN 0 TO 15 LOOP
  38.             a_TB <= STD_LOGIC_VECTOR(to_unsigned(i, 4));
  39.                 FOR j IN 0 TO 15 LOOP
  40.                     b_TB <= STD_LOGIC_VECTOR(to_unsigned(i, 4));
  41.                         FOR k IN 0 TO 1 LOOP
  42.                             sel_TB <= k;
  43.                             WAIT FOR 100 ns;
  44.                         END LOOP;
  45.                 END LOOP;
  46.         END LOOP;
  47.     END PROCESS;
  48. END behavioral;
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