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- --Question #3 (Dean Nguyen)--
- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_UNSIGNED.ALL;
- USE IEEE.NUMERIC_STD.ALL;
- ENTITY Four_Bit_Multi_TB IS
- END Four_Bit_Multi_TB;
- ARCHITECTURE behavioral OF Four_Bit_Multi_TB IS
- COMPONENT Four_Bit_Multi
- PORT( a0, a1, a2, a3, b0, b1, b2, b3, sel : IN STD_LOGIC;
- z0, z1, z2, z3 : OUT STD_LOGIC);
- END COMPONENT;
- --Inputs--
- SIGNAL a_TB : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
- SIGNAL b_TB : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
- SIGNAL sel_TB : STD_LOGIC := '0';
- --Outputs--
- SIGNAL z_TB : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
- BEGIN
- uut: Four_Bit_Multi PORT MAP (
- a0 => a_TB(0),
- a1 => a_TB(1),
- a2 => a_TB(2),
- a3 => a_TB(3),
- b0 => b_TB(0),
- b1 => b_TB(1),
- b2 => b_TB(2),
- b3 => b_TB(3),
- sel => sel_TB,
- z0 => z_TB(0),
- z1 => z_TB(1),
- z2 => z_TB(2),
- z3 => z_TB(3));
- stimulus : PROCESS
- BEGIN
- FOR i IN 0 TO 15 LOOP
- a_TB <= STD_LOGIC_VECTOR(to_unsigned(i, 4));
- FOR j IN 0 TO 15 LOOP
- b_TB <= STD_LOGIC_VECTOR(to_unsigned(i, 4));
- FOR k IN 0 TO 1 LOOP
- sel_TB <= k;
- WAIT FOR 100 ns;
- END LOOP;
- END LOOP;
- END LOOP;
- END PROCESS;
- END behavioral;
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