module villogo(
        input clk,
        input rst,
        input SW0,
        output reg LED
);

reg [26:0] Q;

always @(posedge clk)
begin
    if(rst)
    begin
        LED <= 0;
        Q <= 0;
    end
    else if((!SW0 && Q == 49999999) || (SW0 && Q == 99999999) // trükkös feltétel, de feleakkora a kód :)
    begin
        LED <= ~LED;
        Q <= 0;
    end
    else    Q <= Q +1;
endmodule