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  1. /* Machine-generated using Migen */
  2. module soc(
  3.     output videoin_rst_n,
  4.     input trigger_reset,
  5.     output reg [23:0] adr,
  6.     input clkin,
  7.     output reg tx,
  8.     input [15:0] d,
  9.     output flash_rst_n,
  10.     output oe_n,
  11.     output we_n,
  12.     output ce_n,
  13.     output ac97_rst_n,
  14.     input rx
  15. );
  16.  
  17. reg wishbone_norflash_err_o;
  18. wire csr_we_i;
  19. reg [13:0] csr_from_wishbone_a_o;
  20. wire [1:0] wishbone_lm32d_bte_o;
  21. reg [3:0] tx_count16;
  22. wire [2:0] wishbone_norflash_cti_i;
  23. wire wishbone_to_csr_cyc_i;
  24. wire lm32_I_RTY_I;
  25. wire [13:0] csr_a_i;
  26. reg [15:0] enable16_counter;
  27. wire stat_thre_we;
  28. wire [3:0] wishbone_norflash_sel_i;
  29. wire [1:0] request;
  30. wire [2:0] wishbone_to_csr_cti_i;
  31. wire [29:0] wishbone_norflash_adr_i;
  32. reg [1:0] wb2csr0_counter;
  33. reg [4:0] norflash0_counter;
  34. reg stat_thre;
  35. reg wishbone_norflash_ack_o;
  36. wire [31:0] wishbone_lm32i_dat_i;
  37. reg [2:0] wishbone_shr_cti_o;
  38. reg [7:0] csr_d_o;
  39. wire [1:0] wishbone_norflash_bte_i;
  40. wire [29:0] wishbone_to_csr_adr_i;
  41. wire DCM_SP_RST;
  42. reg tx_busy;
  43. wire [3:0] wishbone_lm32d_sel_o;
  44. wire wishbone_to_csr_stb_i;
  45. wire wishbone_lm32i_cyc_o;
  46. wire [31:0] lm32_D_ADR_O;
  47. wire [31:0] wishbone_shr_dat_i;
  48. wire wishbone_lm32d_stb_o;
  49. wire wishbone_lm32i_err_i;
  50. wire wishbone_lm32i_ack_i;
  51. wire uart0_sel;
  52. wire wishbone_norflash_cyc_i;
  53. reg wishbone_shr_cyc_o;
  54. wire stat_thre_w;
  55. reg [1:0] interconnectshared0_slave_sel_r;
  56. wire [2:0] wishbone_lm32i_cti_o;
  57. wire [1:0] wishbone_to_csr_bte_i;
  58. wire wishbone_norflash_stb_i;
  59. reg wishbone_shr_stb_o;
  60. wire [31:0] wishbone_to_csr_dat_i;
  61. wire wishbone_norflash_we_i;
  62. wire wishbone_shr_ack_i;
  63. reg [31:0] wishbone_shr_dat_o;
  64. wire DCM_SP_PSEN;
  65. reg wishbone_shr_we_o;
  66. reg csr_from_wishbone_we_o;
  67. wire [7:0] csr_d_i;
  68. wire [29:0] wishbone_lm32i_adr_o;
  69. reg [3:0] tx_bitcount;
  70. wire [31:0] wishbone_lm32d_dat_o;
  71. wire [31:0] lm32_I_ADR_O;
  72. reg [1:0] wishbone_shr_bte_o;
  73. wire [31:0] wishbone_norflash_dat_i;
  74. wire rxtx_re;
  75. wire wishbone_shr_err_i;
  76. wire [29:0] wishbone_lm32d_adr_o;
  77. wire [1:0] wishbone_lm32i_bte_o;
  78. wire enable16;
  79. wire lm32_D_RTY_I;
  80. wire [7:0] csr_from_wishbone_d_i;
  81. wire wishbone_lm32d_we_o;
  82. reg [7:0] tx_reg;
  83. reg wishbone_to_csr_err_o;
  84. wire [7:0] divisor_divisor_r;
  85. reg [7:0] divisor_divisor;
  86. reg [31:0] wishbone_to_csr_dat_o;
  87. wire wishbone_lm32d_err_i;
  88. reg grant;
  89. wire [31:0] wishbone_lm32i_dat_o;
  90. wire [3:0] wishbone_to_csr_sel_i;
  91. reg [3:0] wishbone_shr_sel_o;
  92. wire [31:0] wishbone_lm32d_dat_i;
  93. wire [3:0] wishbone_lm32i_sel_o;
  94. reg wishbone_to_csr_ack_o;
  95. wire wishbone_lm32d_cyc_o;
  96. wire [7:0] rxtx_r;
  97. reg [31:0] wishbone_norflash_dat_o;
  98. wire wishbone_lm32i_stb_o;
  99. reg [7:0] csr_from_wishbone_d_o;
  100. reg [29:0] wishbone_shr_adr_o;
  101. wire wishbone_to_csr_we_i;
  102. reg [1:0] interconnectshared0_slave_sel;
  103. wire wishbone_lm32d_ack_i;
  104. reg [7:0] rxtx_w;
  105. wire wishbone_lm32i_we_o;
  106. wire [2:0] wishbone_lm32d_cti_o;
  107.  
  108. // synthesis translate off
  109. reg dummy_s;
  110. initial dummy_s <= 1'b0;
  111. // synthesis translate on
  112. assign lm32_I_RTY_I = 1'd0;
  113. assign lm32_D_RTY_I = 1'd0;
  114. assign wishbone_lm32i_adr_o = lm32_I_ADR_O[31:2];
  115. assign wishbone_lm32d_adr_o = lm32_D_ADR_O[31:2];
  116. assign csr_a_i = csr_from_wishbone_a_o;
  117. assign csr_we_i = csr_from_wishbone_we_o;
  118. assign csr_d_i = csr_from_wishbone_d_o;
  119. assign csr_from_wishbone_d_i = csr_d_o;
  120. assign oe_n = 1'd0;
  121. assign we_n = 1'd1;
  122. assign ce_n = 1'd0;
  123. assign uart0_sel = (csr_a_i[13:9] == 5'd0);
  124. assign rxtx_r = csr_d_i[7:0];
  125. assign rxtx_re = ((uart0_sel & csr_we_i) & (csr_a_i[1:0] == 2'd0));
  126. assign divisor_divisor_r = divisor_divisor;
  127. assign enable16 = (enable16_counter == 16'd0);
  128. assign stat_thre_we = 1'd1;
  129. assign stat_thre_w = (~tx_busy);
  130. assign DCM_SP_PSEN = 1'd0;
  131. assign DCM_SP_RST = 1'd0;
  132.  
  133. // synthesis translate off
  134. reg dummy_d;
  135. // synthesis translate on
  136. always @(*) begin
  137.     wishbone_shr_adr_o <= 30'd0;
  138.     case (grant)
  139.         1'd0: begin
  140.             wishbone_shr_adr_o <= wishbone_lm32i_adr_o;
  141.         end
  142.         default: begin
  143.             wishbone_shr_adr_o <= wishbone_lm32d_adr_o;
  144.         end
  145.     endcase
  146. // synthesis translate off
  147.     dummy_d <= dummy_s;
  148. // synthesis translate on
  149. end
  150.  
  151. // synthesis translate off
  152. reg dummy_d_1;
  153. // synthesis translate on
  154. always @(*) begin
  155.     wishbone_shr_dat_o <= 32'd0;
  156.     case (grant)
  157.         1'd0: begin
  158.             wishbone_shr_dat_o <= wishbone_lm32i_dat_o;
  159.         end
  160.         default: begin
  161.             wishbone_shr_dat_o <= wishbone_lm32d_dat_o;
  162.         end
  163.     endcase
  164. // synthesis translate off
  165.     dummy_d_1 <= dummy_s;
  166. // synthesis translate on
  167. end
  168.  
  169. // synthesis translate off
  170. reg dummy_d_2;
  171. // synthesis translate on
  172. always @(*) begin
  173.     wishbone_shr_sel_o <= 4'd0;
  174.     case (grant)
  175.         1'd0: begin
  176.             wishbone_shr_sel_o <= wishbone_lm32i_sel_o;
  177.         end
  178.         default: begin
  179.             wishbone_shr_sel_o <= wishbone_lm32d_sel_o;
  180.         end
  181.     endcase
  182. // synthesis translate off
  183.     dummy_d_2 <= dummy_s;
  184. // synthesis translate on
  185. end
  186.  
  187. // synthesis translate off
  188. reg dummy_d_3;
  189. // synthesis translate on
  190. always @(*) begin
  191.     wishbone_shr_cyc_o <= 1'd0;
  192.     case (grant)
  193.         1'd0: begin
  194.             wishbone_shr_cyc_o <= wishbone_lm32i_cyc_o;
  195.         end
  196.         default: begin
  197.             wishbone_shr_cyc_o <= wishbone_lm32d_cyc_o;
  198.         end
  199.     endcase
  200. // synthesis translate off
  201.     dummy_d_3 <= dummy_s;
  202. // synthesis translate on
  203. end
  204.  
  205. // synthesis translate off
  206. reg dummy_d_4;
  207. // synthesis translate on
  208. always @(*) begin
  209.     wishbone_shr_stb_o <= 1'd0;
  210.     case (grant)
  211.         1'd0: begin
  212.             wishbone_shr_stb_o <= wishbone_lm32i_stb_o;
  213.         end
  214.         default: begin
  215.             wishbone_shr_stb_o <= wishbone_lm32d_stb_o;
  216.         end
  217.     endcase
  218. // synthesis translate off
  219.     dummy_d_4 <= dummy_s;
  220. // synthesis translate on
  221. end
  222.  
  223. // synthesis translate off
  224. reg dummy_d_5;
  225. // synthesis translate on
  226. always @(*) begin
  227.     wishbone_shr_we_o <= 1'd0;
  228.     case (grant)
  229.         1'd0: begin
  230.             wishbone_shr_we_o <= wishbone_lm32i_we_o;
  231.         end
  232.         default: begin
  233.             wishbone_shr_we_o <= wishbone_lm32d_we_o;
  234.         end
  235.     endcase
  236. // synthesis translate off
  237.     dummy_d_5 <= dummy_s;
  238. // synthesis translate on
  239. end
  240.  
  241. // synthesis translate off
  242. reg dummy_d_6;
  243. // synthesis translate on
  244. always @(*) begin
  245.     wishbone_shr_cti_o <= 3'd0;
  246.     case (grant)
  247.         1'd0: begin
  248.             wishbone_shr_cti_o <= wishbone_lm32i_cti_o;
  249.         end
  250.         default: begin
  251.             wishbone_shr_cti_o <= wishbone_lm32d_cti_o;
  252.         end
  253.     endcase
  254. // synthesis translate off
  255.     dummy_d_6 <= dummy_s;
  256. // synthesis translate on
  257. end
  258.  
  259. // synthesis translate off
  260. reg dummy_d_7;
  261. // synthesis translate on
  262. always @(*) begin
  263.     wishbone_shr_bte_o <= 2'd0;
  264.     case (grant)
  265.         1'd0: begin
  266.             wishbone_shr_bte_o <= wishbone_lm32i_bte_o;
  267.         end
  268.         default: begin
  269.             wishbone_shr_bte_o <= wishbone_lm32d_bte_o;
  270.         end
  271.     endcase
  272. // synthesis translate off
  273.     dummy_d_7 <= dummy_s;
  274. // synthesis translate on
  275. end
  276. assign wishbone_lm32i_dat_i = wishbone_shr_dat_i;
  277. assign wishbone_lm32d_dat_i = wishbone_shr_dat_i;
  278. assign wishbone_lm32i_ack_i = (wishbone_shr_ack_i & (grant == 1'd0));
  279. assign wishbone_lm32d_ack_i = (wishbone_shr_ack_i & (grant == 1'd1));
  280. assign wishbone_lm32i_err_i = (wishbone_shr_err_i & (grant == 1'd0));
  281. assign wishbone_lm32d_err_i = (wishbone_shr_err_i & (grant == 1'd1));
  282. assign request = {wishbone_lm32d_cyc_o, wishbone_lm32i_cyc_o};
  283.  
  284. // synthesis translate off
  285. reg dummy_d_8;
  286. // synthesis translate on
  287. always @(*) begin
  288.     interconnectshared0_slave_sel <= 2'd0;
  289.     interconnectshared0_slave_sel[0] <= (wishbone_shr_adr_o[28:27] == 2'd0);
  290.     interconnectshared0_slave_sel[1] <= (wishbone_shr_adr_o[28:27] == 2'd3);
  291. // synthesis translate off
  292.     dummy_d_8 <= dummy_s;
  293. // synthesis translate on
  294. end
  295. assign wishbone_norflash_adr_i = wishbone_shr_adr_o;
  296. assign wishbone_to_csr_adr_i = wishbone_shr_adr_o;
  297. assign wishbone_norflash_dat_i = wishbone_shr_dat_o;
  298. assign wishbone_to_csr_dat_i = wishbone_shr_dat_o;
  299. assign wishbone_norflash_sel_i = wishbone_shr_sel_o;
  300. assign wishbone_to_csr_sel_i = wishbone_shr_sel_o;
  301. assign wishbone_norflash_stb_i = wishbone_shr_stb_o;
  302. assign wishbone_to_csr_stb_i = wishbone_shr_stb_o;
  303. assign wishbone_norflash_we_i = wishbone_shr_we_o;
  304. assign wishbone_to_csr_we_i = wishbone_shr_we_o;
  305. assign wishbone_norflash_cti_i = wishbone_shr_cti_o;
  306. assign wishbone_to_csr_cti_i = wishbone_shr_cti_o;
  307. assign wishbone_norflash_bte_i = wishbone_shr_bte_o;
  308. assign wishbone_to_csr_bte_i = wishbone_shr_bte_o;
  309. assign wishbone_norflash_cyc_i = (wishbone_shr_cyc_o & interconnectshared0_slave_sel[0]);
  310. assign wishbone_to_csr_cyc_i = (wishbone_shr_cyc_o & interconnectshared0_slave_sel[1]);
  311. assign wishbone_shr_ack_i = (wishbone_norflash_ack_o | wishbone_to_csr_ack_o);
  312. assign wishbone_shr_err_i = (wishbone_norflash_err_o | wishbone_to_csr_err_o);
  313. assign wishbone_shr_dat_i = (({32{interconnectshared0_slave_sel_r[0]}} & wishbone_norflash_dat_o) | ({32{interconnectshared0_slave_sel_r[1]}} & wishbone_to_csr_dat_o));
  314.  
  315. always @(posedge clkout) begin
  316.     if (sys_rst) begin
  317.         wishbone_to_csr_ack_o <= 1'd0;
  318.         grant <= 1'd0;
  319.         tx <= 1'd1;
  320.         interconnectshared0_slave_sel_r <= 2'd0;
  321.         csr_from_wishbone_we_o <= 1'd0;
  322.         wishbone_norflash_dat_o <= 32'd0;
  323.         tx_reg <= 8'd0;
  324.         enable16_counter <= 16'd0;
  325.         csr_from_wishbone_a_o <= 14'd0;
  326.         wb2csr0_counter <= 2'd0;
  327.         norflash0_counter <= 5'd0;
  328.         wishbone_norflash_ack_o <= 1'd0;
  329.         stat_thre <= 1'd0;
  330.         tx_bitcount <= 4'd0;
  331.         csr_from_wishbone_d_o <= 8'd0;
  332.         tx_busy <= 1'd0;
  333.         csr_d_o <= 8'd0;
  334.         tx_count16 <= 4'd0;
  335.         adr <= 24'd0;
  336.         divisor_divisor <= 8'd0;
  337.         wishbone_to_csr_dat_o <= 32'd0;
  338.     end else begin
  339.         csr_from_wishbone_we_o <= 1'd0;
  340.         csr_from_wishbone_d_o <= wishbone_to_csr_dat_i;
  341.         csr_from_wishbone_a_o <= wishbone_to_csr_adr_i[13:0];
  342.         wishbone_to_csr_dat_o <= csr_from_wishbone_d_i;
  343.         if ((wb2csr0_counter == 2'd1)) begin
  344.             csr_from_wishbone_we_o <= wishbone_to_csr_we_i;
  345.         end
  346.         if ((wb2csr0_counter == 2'd2)) begin
  347.             wishbone_to_csr_ack_o <= 1'd1;
  348.         end
  349.         if ((wb2csr0_counter == 2'd3)) begin
  350.             wishbone_to_csr_ack_o <= 1'd0;
  351.         end
  352.         if ((wb2csr0_counter != 2'd0)) begin
  353.             wb2csr0_counter <= (wb2csr0_counter + 2'd1);
  354.         end else begin
  355.             if ((wishbone_to_csr_cyc_i & wishbone_to_csr_stb_i)) begin
  356.                 wb2csr0_counter <= 2'd1;
  357.             end
  358.         end
  359.         if (((wishbone_norflash_cyc_i & wishbone_norflash_stb_i) & (norflash0_counter == 5'd0))) begin
  360.             adr <= {wishbone_norflash_adr_i[22:0], 1'd0};
  361.         end
  362.         if ((norflash0_counter == 5'd12)) begin
  363.             wishbone_norflash_dat_o[31:16] <= d;
  364.             adr <= {wishbone_norflash_adr_i[22:0], 1'd1};
  365.         end
  366.         if ((norflash0_counter == 5'd24)) begin
  367.             wishbone_norflash_dat_o[15:0] <= d;
  368.             wishbone_norflash_ack_o <= 1'd1;
  369.         end
  370.         if ((norflash0_counter == 5'd25)) begin
  371.             wishbone_norflash_ack_o <= 1'd0;
  372.         end
  373.         if ((norflash0_counter == 5'd25)) begin
  374.             norflash0_counter <= 5'd0;
  375.         end else begin
  376.             if ((norflash0_counter != 5'd0)) begin
  377.                 norflash0_counter <= (norflash0_counter + 5'd1);
  378.             end else begin
  379.                 if ((wishbone_norflash_cyc_i & wishbone_norflash_stb_i)) begin
  380.                     norflash0_counter <= 5'd1;
  381.                 end
  382.             end
  383.         end
  384.         if ((uart0_sel & csr_we_i)) begin
  385.             case (csr_a_i[1:0])
  386.                 2'd1: begin
  387.                     divisor_divisor <= csr_d_i[0];
  388.                 end
  389.             endcase
  390.         end
  391.         csr_d_o <= 8'd0;
  392.         if (uart0_sel) begin
  393.             case (csr_a_i[1:0])
  394.                 2'd0: begin
  395.                     csr_d_o <= rxtx_w;
  396.                 end
  397.                 2'd1: begin
  398.                     csr_d_o <= divisor_divisor;
  399.                 end
  400.                 2'd2: begin
  401.                     csr_d_o <= stat_thre;
  402.                 end
  403.             endcase
  404.         end
  405.         if (stat_thre_we) begin
  406.             stat_thre <= stat_thre_w;
  407.         end
  408.         enable16_counter <= (enable16_counter - 1'd1);
  409.         if (enable16) begin
  410.             enable16_counter <= 6'd42;
  411.         end
  412.         if (rxtx_re) begin
  413.             tx_reg <= rxtx_r;
  414.             tx_bitcount <= 1'd0;
  415.             tx_count16 <= 1'd1;
  416.             tx_busy <= 1'd1;
  417.             tx <= 1'd0;
  418.         end else begin
  419.             if ((enable16 & tx_busy)) begin
  420.                 tx_count16 <= (tx_count16 + 1'd1);
  421.                 if ((tx_count16 == 4'd0)) begin
  422.                     tx_bitcount <= (tx_bitcount + 1'd1);
  423.                     if ((tx_bitcount == 4'd8)) begin
  424.                         tx <= 1'd1;
  425.                     end else begin
  426.                         if ((tx_bitcount == 4'd9)) begin
  427.                             tx <= 1'd1;
  428.                             tx_busy <= 1'd0;
  429.                         end else begin
  430.                             tx <= tx_reg[0];
  431.                             tx_reg <= {1'd0, tx_reg[7:1]};
  432.                         end
  433.                     end
  434.                 end
  435.             end
  436.         end
  437.         case (grant)
  438.             1'd0: begin
  439.                 if ((~request[0])) begin
  440.                     if (request[1]) begin
  441.                         grant <= 1'd1;
  442.                     end
  443.                 end
  444.             end
  445.             1'd1: begin
  446.                 if ((~request[1])) begin
  447.                     if (request[0]) begin
  448.                         grant <= 1'd0;
  449.                     end
  450.                 end
  451.             end
  452.         endcase
  453.         interconnectshared0_slave_sel_r <= interconnectshared0_slave_sel;
  454.     end
  455. end
  456.  
  457. lm32_top lm32(
  458.     .I_ERR_I(wishbone_lm32i_err_i),
  459.     .I_DAT_I(wishbone_lm32i_dat_i),
  460.     .D_RTY_I(lm32_D_RTY_I),
  461.     .D_ACK_I(wishbone_lm32d_ack_i),
  462.     .I_ACK_I(wishbone_lm32i_ack_i),
  463.     .D_ERR_I(wishbone_lm32d_err_i),
  464.     .interrupt(interrupt),
  465.     .D_DAT_I(wishbone_lm32d_dat_i),
  466.     .I_RTY_I(lm32_I_RTY_I),
  467.     .I_WE_O(wishbone_lm32i_we_o),
  468.     .I_ADR_O(lm32_I_ADR_O),
  469.     .I_CTI_O(wishbone_lm32i_cti_o),
  470.     .I_BTE_O(wishbone_lm32i_bte_o),
  471.     .D_WE_O(wishbone_lm32d_we_o),
  472.     .D_STB_O(wishbone_lm32d_stb_o),
  473.     .D_BTE_O(wishbone_lm32d_bte_o),
  474.     .I_CYC_O(wishbone_lm32i_cyc_o),
  475.     .D_CYC_O(wishbone_lm32d_cyc_o),
  476.     .D_SEL_O(wishbone_lm32d_sel_o),
  477.     .I_SEL_O(wishbone_lm32i_sel_o),
  478.     .I_LOCK_O(lm32_I_LOCK_O),
  479.     .I_STB_O(wishbone_lm32i_stb_o),
  480.     .I_DAT_O(wishbone_lm32i_dat_o),
  481.     .D_CTI_O(wishbone_lm32d_cti_o),
  482.     .D_DAT_O(wishbone_lm32d_dat_o),
  483.     .D_LOCK_O(lm32_D_LOCK_O),
  484.     .D_ADR_O(lm32_D_ADR_O),
  485.     .clk_i(clkout),
  486.     .rst_i(sys_rst)
  487. );
  488.  
  489. DCM_SP #(
  490.     .CLKDV_DIVIDE(2.0),
  491.     .CLKFX_DIVIDE(5),
  492.     .CLKFX_MULTIPLY(8),
  493.     .CLKIN_DIVIDE_BY_2("FALSE"),
  494.     .CLKIN_PERIOD(20.0),
  495.     .CLKOUT_PHASE_SHIFT("NONE"),
  496.     .CLK_FEEDBACK("NONE"),
  497.     .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
  498.     .DUTY_CYCLE_CORRECTION("TRUE"),
  499.     .PHASE_SHIFT(0),
  500.     .STARTUP_WAIT("TRUE")
  501. ) DCM_SP (
  502.     .RST(DCM_SP_RST),
  503.     .CLKIN(clkin),
  504.     .PSEN(DCM_SP_PSEN),
  505.     .CLKFX(clkout)
  506. );
  507.  
  508. m1reset m1reset(
  509.     .trigger_reset(trigger_reset),
  510.     .flash_rst_n(flash_rst_n),
  511.     .sys_rst(sys_rst),
  512.     .videoin_rst_n(videoin_rst_n),
  513.     .ac97_rst_n(ac97_rst_n),
  514.     .sys_clk(clkout)
  515. );
  516.  
  517. endmodule
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