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Mar 18th, 2018
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VHDL 0.70 KB | None | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. use work.all;
  5.  
  6. entity binarySegment is
  7. port(
  8. bin: in std_logic_vector(3 downto 0);
  9. Sseg: out std_logic_vector(6 downto 0));
  10. end;
  11.  
  12. architecture binary of binarySegment is
  13. begin
  14. with bin select
  15. Sseg <=
  16.  "1000000" when "0000",
  17.  "1111001" when "0001",
  18.  "0100100" when "0010",
  19.  "0110000" when "0011",
  20.  "0011001" when "0100",
  21.  "0010010" when "0101",
  22.  "0000011" when "0110",
  23.  "1111000" when "0111",
  24.  "0000000" when "1000",
  25.  "0011000" when "1001",
  26.  "0001110" when "1010",
  27.  "0000000" when "1011",
  28.  "1000110" when "1100",
  29.  "1000000" when "1101",
  30.  "0000110" when "1110",
  31.  "0001110" when "1111",
  32.  "-------" when others;
  33. end;
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