--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:   18:39:17 05/21/2018
-- Design Name:
-- Module Name:   /home/ise/shared_ise/Projekt/VGA_Mouse/image_tb.vhd
-- Project Name:  VGA_Mouse
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: image1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY image_tb IS
END image_tb;

ARCHITECTURE behavior OF image_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT image1
    PORT(
         clk : IN  std_logic;
         x : IN  std_logic_vector(10 downto 0);
         y : IN  std_logic_vector(9 downto 0);
         datardy : IN  std_logic;
         b1_stat : IN  std_logic_vector(7 downto 0);
         b_x : IN  std_logic_vector(7 downto 0);
         b_y : IN  std_logic_vector(7 downto 0);
         rgb : OUT  std_logic_vector(2 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal clk : std_logic := '0';
   signal x : std_logic_vector(10 downto 0) := (others => '0');
   signal y : std_logic_vector(9 downto 0) := (others => '0');
   signal datardy : std_logic := '0';
   signal b1_stat : std_logic_vector(7 downto 0) := (others => '0');
   signal b_x : std_logic_vector(7 downto 0) := (others => '0');
   signal b_y : std_logic_vector(7 downto 0) := (others => '0');

    --Outputs
   signal rgb : std_logic_vector(2 downto 0);

   -- Clock period definitions
   constant clk_period : time := 2 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: image1 PORT MAP (
          clk => clk,
          x => x,
          y => y,
          datardy => datardy,
          b1_stat => b1_stat,
          b_x => b_x,
          b_y => b_y,
          rgb => rgb
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.

        y <= std_logic_vector ( unsigned ( y ) + 10 );


        for i in 1 to 600 loop
            datardy <= '1';
           x <= std_logic_vector ( unsigned ( x ) + 1 );
            --y <= std_logic_vector ( unsigned ( y ) + 1 );
            b_x <= std_logic_vector ( unsigned ( y ) + 1 );
            --b_y <= std_logic_vector ( unsigned ( y ) + 1 );
            wait for 2ns;
            datardy <= '0';
        end loop;


      wait;
   end process;

END;