library ieee;use ieee.std_logic_1164.all;entity test_state isport ( clk : in std_ulogic;reset : in std_ulogic;con1, con2, con3 : in std_ulogic;out1, out2 : out std_ulogic );end test_state;--------------------------------------------------------------------------------- MOORE machine (outputs come from CASE statment)-------------------------------------------------------------------------------architecture rtl of test_state istype state_type is (s0, s1, s2, s3);signal state, next_state : state_type;begin -- rtlstate_encode : process ( state, con1, con2, con3 )beginnext_state <= s1;case state iswhen s0 =>next_state <= s1;when s1 =>if ( con1 = '1' ) thennext_state <= s2;elsenext_state <= s1;end if;when s2 =>next_state <= s3;when s3 =>if ( con2 = '0' ) thennext_state <= s3;elsif ( con3 = '0' ) thennext_state <= s2;elsenext_state <= s0;end if;end case;end process state_encode;state_register : process ( reset, clk )beginif ( reset = '0' ) thenstate <= s0;elsif ( clk'event and clk = '1' ) thenstate <= next_state;end if;end process state_register;state_decode : process ( state, con1, con2, con3 )begincase state iswhen s0 =>out1 <= '0';

out2 <= '0';when s1 =>out1 <= '1';out2 <= '0';when s2 =>out1 <= '0';out2 <= '1';when s3 =>if ( con2 = '0' ) thenout1 <= '0';out2 <= '0';elsif ( con3 = '0' ) thenout1 <= '0';out2 <= '1';elseout1 <= '1';out2 <= '1';end if;end case;end process state_decode;