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nick

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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.NUMERIC_STD.ALL;
  4.  
  5. entity reg is
  6.   generic(
  7.     wordSize: natural :=4
  8.   );
  9.   port(
  10.     clock, reset, load: in bit;
  11.     d: in bit_vector(wordSize-1 downto 0);
  12.     q: out bit_vector(wordSize-1 downto 0)
  13.   );
  14. end reg;
  15.  
  16. architecture arch of reg is
  17. begin
  18.   process(clock, reset, load)
  19.   begin
  20.     if (reset = '1') then
  21.       q <= (others => '0');
  22.     elsif (clock'event and clock='1') then
  23.       if (load='1') then
  24.         q <= d;
  25.       end if;
  26.     end if;
  27.   end process;
  28. end arch;
  29.  
  30. library IEEE;
  31. use IEEE.STD_LOGIC_1164.ALL;
  32. use IEEE.NUMERIC_BIT.ALL;
  33. use IEEE.MATH_REAL.CEIL;
  34. use IEEE.MATH_REAL.LOG2;
  35.  
  36. entity regfile is
  37.   generic(
  38.     regn: natural := 32;
  39.     wordSize: natural := 64
  40.   );
  41.   port(
  42.     clock, reset, regWrite : in bit;
  43.     rr1, rr2, wr: in bit_vector(natural(ceil(log2(real(regn))))-1 downto 0);
  44.     d: in bit_vector(wordSize-1 downto 0);
  45.     q1, q2: out bit_vector(wordSize-1 downto 0)
  46.   );
  47. end regfile;
  48.  
  49. architecture behavioral of regfile is
  50.   component reg is
  51.         generic (
  52.             wordSize : natural := 4
  53.         );
  54.         port (
  55.             clock, reset, load : in bit;
  56.             d : in bit_vector(wordSize - 1 downto 0);
  57.             q : out bit_vector(wordSize - 1 downto 0)
  58.         );
  59.   end component;
  60.   type registerFile is array(regn-1 downto 0) of bit_vector(wordSize-1 downto 0);
  61.     signal write : registerFile;
  62.     signal read : registerFile;
  63.     signal zero : bit_vector (wordSize-1 downto 0);
  64. begin
  65.   gen: for i in 0 to regn-2 generate
  66.     Rf: reg generic map (wordSize => wordSize)
  67.           port map (clock, reset, regWrite, write(i), read(i));
  68.   end generate gen;
  69.   Rz: reg generic map (wordSize => wordSize)
  70.         port map(clock, reset, regWrite, zero, read(regn-1));
  71.   q1 <= read(to_integer(unsigned(rr1)));
  72.   q2 <= read(to_integer(unsigned(rr2)));
  73.   write(to_integer(unsigned(wr))) <= d;
  74.  
  75. end behavioral;
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