Contador Completo

library IEEE;
use IEEE.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity Contador_Completo is --Contador implementado en la Board
port (
    Up_Down, Clk_Manual, Clk_100Hz,Clk: IN  std_logic;
    U,D,OvF : Out std_logic;
    BCD_Out : OUT std_logic_vector(3 downto 0);
    Q_Out :  OUT std_logic_vector(3 downto 0)
);
end Contador_Completo;

architecture architecture_Contador_Completo of Contador_Completo is

    signal Clock, Clock_M , UD , U_D : std_logic;
    signal Qaux : std_logic_vector(3 downto 0) ;

    component Contador is
    Port ( UP_DW : in  STD_LOGIC;
           CLK_in : in  STD_LOGIC;
           Q : out std_logic_vector (3 downto 0)
             );
    end component;

    component Conversor_BDC is
    Port ( Q : in  STD_LOGIC_VECTOR (3 downto 0);
           OverF : out std_logic;
           BCD : out  STD_LOGIC_VECTOR (3 downto 0));
    end component;

    component FF_T is
    port (
        T : IN  std_logic;
        Q : OUT std_logic);
     end component;

    Component Antirrebote_100Hz is
    Port ( S_in : in  STD_LOGIC;
           S_out : out  STD_LOGIC;
           Clk : in  STD_LOGIC);
    end component;

begin

    Clock <= Clk or not(Clock_M);
    Q_Out <= not Qaux;
    U <= not U_D;
    D <= U_D;

    CONT : Contador Port map(
    UP_DW => U_D,
    CLK_in => CLock,
    Q => Qaux);

    BCD : Conversor_BDC port map (
    Q => Qaux,
    OverF => OvF,
    BCD => BCD_Out);

    AntRClk : Antirrebote_100Hz Port map (
    S_in => Clk_Manual,
    S_Out => Clock_M,
    Clk => Clk_100Hz);

    AntRUD : Antirrebote_100Hz Port map (
    S_in => Up_Down,
    S_Out => UD,
    Clk => Clk_100Hz);

    FFT : FF_T port map(
    T => UD,
    Q => U_D);



end architecture_Contador_Completo;