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  1. // WARNING: Do NOT edit the input and output ports in this file in a text
  2. // editor if you plan to continue editing the block that represents it in
  3. // the Block Editor! File corruption is VERY likely to occur.
  4.  
  5. // Copyright (C) 1991-2010 Altera Corporation
  6. // Your use of Altera Corporation's design tools, logic functions
  7. // and other software and tools, and its AMPP partner logic
  8. // functions, and any output files from any of the foregoing
  9. // (including device programming or simulation files), and any
  10. // associated documentation or information are expressly subject
  11. // to the terms and conditions of the Altera Program License
  12. // Subscription Agreement, Altera MegaCore Function License
  13. // Agreement, or other applicable license agreement, including,
  14. // without limitation, that your use is for the sole purpose of
  15. // programming logic devices manufactured by Altera and sold by
  16. // Altera or its authorized distributors. Please refer to the
  17. // applicable agreement for further details.
  18.  
  19.  
  20. // Generated by Quartus II Version 10.0 (Build Build 218 06/27/2010)
  21. // Created on Sat Oct 23 22:13:27 2010
  22.  
  23. // Module Declaration
  24. module ALU
  25. (
  26. // {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
  27. reg1, reg2, ctrl, out
  28. // {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
  29. );
  30. // Port Declaration
  31.  
  32. // {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
  33. input reg1;
  34. input reg2;
  35. input ctrl;
  36. output out;
  37. // {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
  38.  
  39.  
  40. assign out = (ctrl == 0 && reg2 == 0) ? reg1 >> 1 :
  41. (ctrl == 0 && reg2 != 0) ? reg1 << 1 :
  42. (ctrl == 1) ? reg1 + reg2 :
  43. (ctrl == 2) ? reg1 - reg2 :
  44. (ctrl == 3) ? reg1 & reg2 :
  45. (ctrl == 4) ? reg1 | (1 << reg2) : 1'bx;
  46. endmodule
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