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- // WARNING: Do NOT edit the input and output ports in this file in a text
- // editor if you plan to continue editing the block that represents it in
- // the Block Editor! File corruption is VERY likely to occur.
- // Copyright (C) 1991-2010 Altera Corporation
- // Your use of Altera Corporation's design tools, logic functions
- // and other software and tools, and its AMPP partner logic
- // functions, and any output files from any of the foregoing
- // (including device programming or simulation files), and any
- // associated documentation or information are expressly subject
- // to the terms and conditions of the Altera Program License
- // Subscription Agreement, Altera MegaCore Function License
- // Agreement, or other applicable license agreement, including,
- // without limitation, that your use is for the sole purpose of
- // programming logic devices manufactured by Altera and sold by
- // Altera or its authorized distributors. Please refer to the
- // applicable agreement for further details.
- // Generated by Quartus II Version 10.0 (Build Build 218 06/27/2010)
- // Created on Sat Oct 23 22:13:27 2010
- // Module Declaration
- module ALU
- (
- // {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
- reg1, reg2, ctrl, out
- // {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
- );
- // Port Declaration
- // {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
- input reg1;
- input reg2;
- input ctrl;
- output out;
- // {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
- assign out = (ctrl == 0 && reg2 == 0) ? reg1 >> 1 :
- (ctrl == 0 && reg2 != 0) ? reg1 << 1 :
- (ctrl == 1) ? reg1 + reg2 :
- (ctrl == 2) ? reg1 - reg2 :
- (ctrl == 3) ? reg1 & reg2 :
- (ctrl == 4) ? reg1 | (1 << reg2) : 1'bx;
- endmodule
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