module pwm(
    input clk,
    input [3:0] amt,
    output reg out
);

reg [3:0] cnt;

always @(posedge clk) begin
    {out, cnt} <= cnt + amt;
end

endmodule


module main(
    input hclk,
    output [3:0] vgaRed,
    output [3:0] vgaGreen,
    output [3:0] vgaBlue,
    output Vsync,
    output Hsync,
    input btnC,
    input btnU,
    input btnL,
    input btnR,
    input btnD,
    input [15:0] sw,
    output [15:0] led
);

wire feedback, clk, clk_pwm;

PLLE2_BASE #(
    .CLKFBOUT_MULT(12), // Multiply value for all CLKOUT, (2-64)
    .CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
    .CLKOUT0_DIVIDE(4),
    .CLKOUT1_DIVIDE(2),
    .DIVCLK_DIVIDE(1),
    .STARTUP_WAIT("TRUE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) PLLE2_BASE_inst (
    .CLKOUT0(clk),
    .CLKOUT1(clk_pwm),
    .CLKFBOUT(feedback), // 1-bit output: Feedback clock
    .CLKIN1(hclk),
    .CLKFBIN(feedback) // 1-bit input: Feedback clock
);

pwm(clk_pwm, sw[3:0], led[15]);

endmodule