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  1. `define push        2'b00
  2. `define pop         2'b01
  3. `define push_prev   2'b10
  4. `define idle        2'b11
  5. `define IDLE        1'b0
  6. `define WORK        1'b1
  7.  
  8. module queue(clk,reset,go,cmd,r_num,ready,w_en,r_en,full,almost_full,empty,almost_empty,error,w_num,addr);
  9.     input clk,reset,go;
  10.     input [17:0]cmd;
  11.     input [15:0]r_num;
  12.  
  13.     output reg ready;
  14.     output w_en,r_en;
  15.     output full,almost_full,empty,almost_empty,error;
  16.     output [15:0]w_num;
  17.     output [4:0]addr;
  18.  
  19.     reg state, next_state;
  20.     reg [15:0]pop_num, next_pop_num;
  21.     reg [4:0]r_ad, next_r_ad, w_ad, next_w_ad, ad, next_ad;
  22.     reg pop_check, next_pop_check, full_check, next_full_check;
  23.  
  24.     always@(posedge reset or posedge clk)begin
  25.         if(reset == 1'b1)begin
  26.             state <= `IDLE;
  27.             ad <= 5'd0;
  28.             r_ad <= 5'd0;
  29.             w_ad <= 5'd0;
  30.             pop_check <= 1'b0;
  31.             full_check <= 1'b0;
  32.         end
  33.         else begin
  34.             state <= next_state;
  35.             pop_num <= next_pop_num;
  36.             ad <= next_ad;
  37.             r_ad <= next_r_ad;
  38.             w_ad <= next_w_ad;
  39.             pop_check <= next_pop_check;
  40.             full_check <= next_full_check;
  41.         end
  42.     end
  43.  
  44.     always@(posedge clk)begin
  45.         next_state = state;
  46.         next_pop_num = pop_num;
  47.         next_ad = ad;
  48.         next_r_ad = r_ad;
  49.         next_w_ad = w_ad;
  50.         next_pop_check = pop_check;
  51.         next_full_check = full_check;
  52.         ready = (go == 1'b1 ? 1'b0 : 1'b1);
  53.         case(state)
  54.             `IDLE:begin
  55.                 next_state = (go == 1'b1 ? 1'b1 : 1'b0);
  56.             end
  57.             `WORK:begin
  58.                 next_state = (go == 1'b1 ? 1'b1 : 1'b0);
  59.                 if(cmd[17:16] == `push)begin
  60.                     next_pop_num = pop_num;
  61.                     next_ad = w_ad;
  62.                     next_r_ad = r_ad;
  63.                     next_w_ad = (w_ad == 5'd31 ? 5'd0 : w_ad+1);
  64.                     next_pop_check = pop_check;
  65.                     next_full_check = (w_ad == r_ad-1 ? 1'b1 : 1'b0);
  66.                 end
  67.                 else if(cmd[17:16] == `pop)begin
  68.                     next_pop_num = cmd[15:0];
  69.                     next_ad = r_ad;
  70.                     next_r_ad = (r_ad == 5'd31 ? 5'd0 : r_ad+1);
  71.                     next_w_ad = w_ad;
  72.                     next_pop_check = 1'b1;
  73.                     next_full_check = 1'b0;
  74.                 end
  75.                 else if(cmd[17:16] == `push_prev)begin
  76.                     next_pop_num = pop_num;
  77.                     next_ad = w_ad;
  78.                     next_r_ad = r_ad;
  79.                     next_w_ad = (w_ad == 5'd31 ? 5'd0 : w_ad+1);
  80.                     next_pop_check = pop_check;
  81.                     next_full_check = full_check;
  82.                 end
  83.                 else if(cmd[17:16] == `idle)begin
  84.                    
  85.                 end    
  86.             end
  87.         endcase
  88.         if(error == 1'b1 && state == `pop)begin
  89.             r_ad = (r_ad == 5'd0 ? 5'd31 : r_ad-1);
  90.         end
  91.         else if(error == 1'b1 && (state == `push || state == `push_prev))begin
  92.             w_ad = (w_ad == 5'd0 ? 5'd31 : w_ad-1);
  93.         end
  94.     end
  95.    
  96.     assign w_en = (state == `push || state == `push_prev) ? 1'b1 : 1'b0;
  97.     assign r_en = (state == `pop) ? 1'b1 : 1'b0;
  98.     assign full = (full_check == 1'b1) ? 1'b1 : 1'b0;
  99.     assign almost_full = (w_ad == r_ad-1 || (w_ad == 5'd31 && r_ad == 5'd0)) ? 1'b1 : 1'b0;
  100.     assign empty = (w_ad == r_ad && full_check == 1'b0) ? 1'b1 : 1'b0;
  101.     assign almost_empty = (w_ad == r_ad+1 || (w_ad == 5'd0 && r_ad == 5'd31)) ? 1'b1 : 1'b0;
  102.     assign error = ((full == 1'b1 && (state == `push || state == `push_prev)) ||  (pop_check == 1'b0 && state == `push_prev) ||
  103.                     (empty == 1'b1 && state == `pop)) ? 1'b1 : 1'b0;
  104.     assign w_num = (w_en == 1'b1) ? cmd[15:0] : 16'dX;
  105.     assign addr = ad;
  106.    
  107. endmodule
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