Q25227.vhd Source
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY Q25227 IS
    PORT(A, B   : IN STD_LOGIC;
        Y       : OUT STD_LOGIC);
END Q25227;

-- OR gate behaviour with conditional logic
ARCHITECTURE csa OF Q25227 IS
BEGIN
Y <=    '1' WHEN A = '1' ELSE
        '1' WHEN B = '1' ELSE
        '0';
END csa;