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Jul 19th, 2019
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  1. localparam CLK10HZ_THRESH = 50_000_000 / 10;
  2.  
  3. reg clk10hz_en;
  4. reg [$clog2(CLK10HZ_THRESH):0] clk10hz_counter;
  5.  
  6. initial clk10hz_en = 0;
  7. initial clk10hz_counter = 0;
  8.  
  9. reg [3:0] state;
  10. initial state = 0;
  11.  
  12. reg [7:0] led_state;
  13. initial led_state = 0;
  14.  
  15. assign LED = led_state;
  16.  
  17. always @(posedge FPGA_CLK1_50) begin
  18.    clk10hz_en <= 1'b0;
  19.    if (clk10hz_counter == CLK10HZ_THRESH - 1)
  20.    begin
  21.       clk10hz_counter <= 0;
  22.       clk10hz_en <= 1'b1;
  23.    end
  24.    else
  25.       clk10hz_counter <= clk10hz_counter + 1'b1;
  26. end
  27.  
  28. always @(posedge FPGA_CLK1_50) begin
  29.    if (clk10hz_en)
  30.       state = state + 1'b1;
  31. end
  32.  
  33. integer ii;
  34.  
  35. generate
  36. always @(*) begin
  37.    for (ii = 0; ii < 8; ii = ii + 1)
  38.       led_state[ii] = (state == ii || state == 15 - ii);
  39. end
  40. endgenerate
  41.    
  42. endmodule
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