SHARE
TWEET

Untitled

a guest May 19th, 2017 45 Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    14:28:13 03/23/2017
  6. -- Design Name:
  7. -- Module Name:    Id - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22.  
  23. -- Uncomment the following library declaration if using
  24. -- arithmetic functions with Signed or Unsigned values
  25. --use IEEE.NUMERIC_STD.ALL;
  26.  
  27. -- Uncomment the following library declaration if instantiating
  28. -- any Xilinx primitives in this code.
  29. --library UNISIM;
  30. --use UNISIM.VComponents.all;
  31.  
  32. entity Id is
  33.     Port ( X : in  STD_LOGIC_VECTOR (63 downto 0);
  34.            Y : out  STD_LOGIC_VECTOR (63 downto 0));
  35. end Id;
  36.  
  37. architecture Behavioral of Id is
  38.     component P is
  39.          Port ( X : in  STD_LOGIC_VECTOR (63 downto 0);
  40.                   Y : out  STD_LOGIC_VECTOR (63 downto 0));
  41.     end component P;
  42.     component NL is
  43.          Port ( X : in  STD_LOGIC_VECTOR (63 downto 0);
  44.                   Ka : in  STD_LOGIC_VECTOR (63 downto 0);
  45.                   Kb : in  STD_LOGIC_VECTOR (63 downto 0);
  46.                   Y : out  STD_LOGIC_VECTOR (63 downto 0));
  47.     end component NL;
  48.     component NLi is
  49.          Port ( X : in  STD_LOGIC_VECTOR (63 downto 0);
  50.                   Ka : in  STD_LOGIC_VECTOR (63 downto 0);
  51.                   Kb : in  STD_LOGIC_VECTOR (63 downto 0);
  52.                   Y : out  STD_LOGIC_VECTOR (63 downto 0));
  53.     end component NLi;
  54.     component KeyGen is
  55.          Port ( Y : out  STD_LOGIC_VECTOR (511 downto 0));
  56.     end component KeyGen;  
  57.     signal buff : STD_LOGIC_VECTOR (63 downto 0);
  58.     signal buffi : STD_LOGIC_VECTOR (63 downto 0);
  59.     signal buff1 : STD_LOGIC_VECTOR (63 downto 0);
  60.     signal buffi1 : STD_LOGIC_VECTOR (63 downto 0);
  61.     signal buff2 : STD_LOGIC_VECTOR (63 downto 0);
  62.     signal buffi2 : STD_LOGIC_VECTOR (63 downto 0);
  63.     signal buff3 : STD_LOGIC_VECTOR (63 downto 0);
  64.     signal buffi3 : STD_LOGIC_VECTOR (63 downto 0);
  65.     signal buff4 : STD_LOGIC_VECTOR (63 downto 0);
  66.     signal buffi4 : STD_LOGIC_VECTOR (63 downto 0);
  67.     signal buff5 : STD_LOGIC_VECTOR (63 downto 0);
  68.     signal buffi5 : STD_LOGIC_VECTOR (63 downto 0);
  69.     signal buff6 : STD_LOGIC_VECTOR (63 downto 0);
  70.     signal buffi6 : STD_LOGIC_VECTOR (63 downto 0);
  71.     signal buff7 : STD_LOGIC_VECTOR (63 downto 0);
  72.     signal buffi7 : STD_LOGIC_VECTOR (63 downto 0);
  73.     signal key : STD_LOGIC_VECTOR (511 downto 0);
  74.     signal checker1 : STD_LOGIC_VECTOR (63 downto 0);
  75.     signal checker2 : STD_LOGIC_VECTOR (63 downto 0);
  76.     signal checker3 : STD_LOGIC_VECTOR (63 downto 0);
  77.     signal checker4 : STD_LOGIC_VECTOR (63 downto 0);
  78. begin
  79.     b0: KeyGen port map (key);
  80.     b1: NL port map (X, key(511 downto 448), key(447 downto 384), buff);
  81.     b2: P port map (buff, buffi);
  82.     b3: NL port map (buffi, key(383 downto 320), key(319 downto 256), buff1);
  83.     b4: P port map (buff1, buffi1);
  84.     b5: NL port map (buffi1, key(255 downto 192), key(191 downto 128), buff2);
  85.     b6: P port map (buff2, buffi2);
  86.     b7: NL port map (buffi2, key(127 downto 64), key(63 downto 0), buff3);
  87.     b8: P port map (buff3, buffi3);
  88.     b9: buff4 <= buffi3;
  89.     b10: P port map (buff4, buffi4);
  90.     b11: NLi port map (buffi4, key(127 downto 64), key(63 downto 0), buff5);
  91.     b12: P port map (buff5, buffi5);
  92.     b13: NLi port map (buffi5, key(255 downto 192), key(191 downto 128), buff6);
  93.     b14: P port map (buff6, buffi6);
  94.     b15: NLi port map (buffi6, key(383 downto 320), key(319 downto 256), buff7);
  95.     b16: P port map (buff7, buffi7);
  96.     b17: NLi port map (buffi7, key(511 downto 448), key(447 downto 384), Y);
  97.    
  98.     b18: checker1 <=  buff XOR Y;
  99.     b19: checker2 <=  buff1 XOR buff7;
  100.     b20: checker3 <=  buff2 XOR buff6;
  101.     b21: checker4 <=  buff3 XOR buff5;
  102.    
  103. end Behavioral;
RAW Paste Data
Top