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-- Company:
-- Engineer:
--
-- Create Date: 03/15/2018 10:15:11 AM
-- Design Name:
-- Module Name: 8BitRippleCarryFulladder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity EightBitFulladder is
    Port ( Ain : in STD_LOGIC_VECTOR (7 downto 0);
           Bin : in STD_LOGIC_VECTOR (7 downto 0);
           Cin : in STD_LOGIC;
           Cout : out STD_LOGIC;
           ResultOut : out STD_LOGIC_VECTOR (7 downto 0);
           CLK : in STD_LOGIC);
end EightBitFulladder;

Architecture EightBitFulladder of adder8 is
        signal c1, c2, c3, c4	:		Std_logic;
        signal c5, c6, c7	:		Std_logic;


component Fulladder
    Port ( Ain : in STD_LOGIC;
       Bin : in STD_LOGIC;
       Cin : in STD_LOGIC;
       Sout : out STD_LOGIC;
       Cout : out STD_LOGIC
       );
end component Fulladder;
begin
	U32_0: entity WORK.Fulladder port map (Ain <= Ain[0], Bin <= Bin[0], Cin <= Cin, Cout <= c1,  Sout <= ResultOut[0]);
	U32_1: entity WORK.Fulladder port map (Ain <= Ain[1], Bin <= Bin[1], Cin <= c1, Cout <= c2,   Sout <= ResultOut[1]);
	U32_2: entity WORK.Fulladder port map (Ain <= Ain[2], Bin <= Bin[2], Cin <= c2, Cout <= c3,   Sout <= ResultOut[2]);
	U32_3: entity WORK.Fulladder port map (Ain <= Ain[3], Bin <= Bin[3], Cin <= c3, Cout <= c4,   Sout <= ResultOut[3]);
	U32_4: entity WORK.Fulladder port map (Ain <= Ain[4], Bin <= Bin[4], Cin <= c4, Cout <= c5,   Sout <= ResultOut[4]);
	U32_5: entity WORK.Fulladder port map (Ain <= Ain[5], Bin <= Bin[5], Cin <= c5, Cout <= c6,   Sout <= ResultOut[5]);
	U32_6: entity WORK.Fulladder port map (Ain <= Ain[6], Bin <= Bin[6], Cin <= c6, Cout <= c7,   Sout <= ResultOut[6]);
	U32_7: entity WORK.Fulladder port map (Ain <= Ain[7], Bin <= Bin[7], Cin <= c7, Cout <= Cout, Sout <= ResultOut[7]);


end Behavioral;