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May 26th, 2017
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VHDL 0.25 KB | None | 0 0
  1.     fifo_rdack <= fifo_valid when payload_count < 16 else '0';
  2.     process(clock, reset)
  3.     begin
  4.         if rising_edge(clock) then
  5.             if fifo_rdack = '1' then
  6.                 payload_count <= payload_count + 1;
  7.                 foo <= fifo_dout;
  8.             end if;
  9.         end if;
  10.     end process;
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