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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 14.04.2018 18:58:29
  7. // Design Name:
  8. // Module Name: FSM
  9. // Project Name:
  10. // Target Devices:
  11. // Tool Versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21.  
  22.  
  23. module FSM(input L, R, clk, rst, output reg [5:0] LIGHTS);
  24.  
  25. //localparam S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6;
  26. //reg [2:0] state_p, // Current state
  27. //state_n; // Next state
  28. parameter IDLE = 6'b000000, // Output-coded state assignment
  29.           L3 = 6'b111000, // and tail-light patterns
  30.           L2 = 6'b011000,
  31.           L1 = 6'b001000,
  32.           R1 = 6'b000100,
  33.           R2 = 6'b000110,
  34.           R3 = 6'b000111;
  35.          
  36. clk_div clk_div(clk, rst, clk_en);
  37.  
  38.  always @ (clk_en)
  39.  begin
  40.  if (rst) LIGHTS <= IDLE; else
  41.     case (LIGHTS)
  42.     IDLE : if(L) LIGHTS <= L1;
  43.            else if (R) LIGHTS <= R1;
  44.            else LIGHTS <= IDLE;
  45.     L1 :     LIGHTS <= L2;
  46.     L2 :     LIGHTS <= L3;
  47.     L3 :     LIGHTS <= IDLE;
  48.     R1 :     LIGHTS <= R2;
  49.     R2 :     LIGHTS <= R3;
  50.     R3 :     LIGHTS <= IDLE;    
  51.  default : ;
  52.  endcase
  53.  end
  54.  
  55. /* always @(clk_en) begin
  56.  if (rst) begin
  57.  state_p <= S0; // Initial state
  58.  end else begin
  59.  state_p <= state_n;
  60.  end
  61. end
  62.  
  63. always@(*) begin
  64.  // state_n <= state_p;
  65.  case (state_p)
  66.  
  67.  S0: begin
  68.     TL <= 3'b000;
  69.     TR <= 3'b000;
  70.    
  71.     if (L == 1) begin
  72.     state_n <= S1;
  73.     end
  74.    
  75.     else if (R == 1) begin
  76.     state_n <= S4;
  77.     end
  78.    
  79.     end
  80.    
  81.  S1: begin  
  82.     TL <= 3'b001;
  83.     state_n <= S2;
  84.     end
  85.    
  86.  S2: begin
  87.     TL <= 3'b011;
  88.     state_n <= S3;
  89.     end
  90.    
  91.  S3: begin
  92.     TL <= 3'b111;
  93.     state_n <= S0;
  94.     end
  95.    
  96.  S4: begin
  97.     TR <= 3'b100;
  98.     state_n <= S5;
  99.     end
  100.    
  101.  S5: begin
  102.     TR <= 3'b110;
  103.     state_n <= S6;
  104.     end
  105.    
  106.  S6: begin
  107.     TR <= 3'b111;
  108.     state_n <= S0;
  109.     end
  110.    
  111.  default: begin
  112.     TL <= 3'b000;
  113.     TR <= 3'b000;
  114.     end
  115.  
  116.  endcase
  117. end
  118. */
  119.  
  120. endmodule
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