module counter(SW, HEX, KEY);
    input [2:0] SW;
    input [0] KEY;
    output [6:0] HEX0, HEX1;
    wire [3:0] w0, w1;

    bcounter8 bc0(
        .Enable(SW[1]),
        .Clock(KEY[0]),
        .Clear_b(SW[0]),
        .q({w1, w0})
    );

    seven_seg_decoder s0(
        .b(w0),
        .a(HEX0)
    );

    seven_seg_decoder s1(
        .b(w1),
        .a(HEX1)
    );

endmodule


module bcounter8(Enable, Clock, Clear_b, q)

    input Enable, Clock, Clear_b;
    output [7:0] q;

    wire w1, w2, w3, w4, w5, w6, w7;

    assign w1 = q[0] & Enable;
    assign w2 = w1 & q[1];
    assign w3 = w2 & q[2];
    assign w4 = w3 & q[3];
    assign w5 = w4 & q[4];
    assign w6 = w5 & q[5];
    assign w7 = w6 & q[6];


    tflipflop t0(
        .t(Enable),
        .clk(Clock),
        .reset_n(Clear_b),
        .q(q[0])
    );

    tflipflop t1(
        .t(w1),
        .clk(Clock),
        .reset_n(Clear_b),
        .q(q[1])
    );

    tflipflop t2(
        .t(w2),
        .clk(Clock),
        .reset_n(Clear_b),
        .q(q[2])
    );

    tflipflop t3(
        .t(w3),
        .clk(Clock),
        .reset_n(Clear_b),
        .q(q[3])
    );

    tflipflop t4(
        .t(w4),
        .clk(Clock),
        .reset_n(Clear_b),
        .q(q[4])
    );

    tflipflop t5(
        .t(w5),
        .clk(Clock),
        .reset_n(Clear_b),
        .q(q[5])
    );

    tflipflop t6(
        .t(w6),
        .clk(Clock),
        .reset_n(Clear_b),
        .q(q[6])
    );

    tflipflop t7(
        .t(w7),
        .clk(Clock),
        .reset_n(Clear_b),
        .q(q[7])
    );
endmodule

module tflipflop(t, clk, reset_n, q);
    input t, clk, reset_n;
    output reg q;

    always @ (posedge clk, negedge reset_n)
    begin
        if (reset_n == 1'b0)
            q <= 1'b0;
        else if (t == 1'b1)
            q <= ~q;

    end
endmodule

module seven_seg_decoder(a,b);
    input [3:0]b;
    output [6:0]a;

    assign a[0] = (~b[3]&b[2]&~b[1]&~b[0])|(~b[3]&~b[2]&~b[1]&b[0])|(b[3]&b[2]&~b[1]&b[0])|(b[3]&~b[2]&b[1]&b[0]);
    assign a[1] = (~b[3]&b[2]&~b[1]&b[0])|(b[3]&b[1]&b[0])|(b[2]&b[1]&~b[0])|(b[3]&b[2]&~b[0]);
    assign a[2] = (~b[3]&~b[2]&b[1]&~b[0])|(b[3]&b[2]&b[1])|(b[3]&b[2]&~b[0]);
    assign a[3] = (~b[3]&b[2]&~b[1]&~b[0])|(~b[2]&~b[1]&b[0])|(b[2]&b[1]&b[0])|(b[3]&~b[2]&b[1]&~b[0]);
    assign a[4] = (~b[3]&b[2]&~b[1])|(~b[2]&~b[1]&b[0])|(~b[3]&b[0]);
    assign a[5] = (b[3]&b[2]&~b[1]&b[0])|(~b[3]&~b[2]&b[0])|(~b[3]&b[1]&b[0])|(~b[3]&~b[2]&b[1]);
    assign a[6] = (~b[3]&~b[2]&~b[1])|(b[3]&b[2]&~b[1]&~b[0])|(~b[3]&b[2]&b[1]&b[0]);

endmodule