library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
port(
	ledr : out std_logic;
	clk50,reset_n,rx_in, key2, key1 : in std_logic
);
end entity;

architecture str of top_level is

	signal data_int : std_logic_vector(7 downto 0);
	signal valid_int : std_logic;

component serial_uart is
	generic(
      g_reset_active_state    : std_logic                      := '0'; --changed to active low
      g_serial_speed_bps      : natural range 9600 to 115200   := 9600;
      g_clk_period_ns         : natural range 10 to 100        := 20;      -- 50 MHz standard clock
      g_parity                : natural range 0 to 2           := 0);      -- 0 = no, 1 = odd, 2 = even
   port(
      clk                     : in  std_logic;
      reset                   : in  std_logic;   -- active high reset
      rx                      : in  std_logic;
      tx                      : out std_logic;

      received_data           : out std_logic_vector(7 downto 0); -- Received data
      received_valid          : out std_logic;  -- Set high one clock cycle when byte is received.
      received_error          : out std_logic;  -- Stop bit was not high
      received_parity_error   : out std_logic;  -- Parity error detected

      transmit_ready          : out std_logic;
      transmit_valid          : in  std_logic;
      transmit_data           : in  std_logic_vector(7 downto 0));
end component serial_uart;

component oled_ctrl is
	port(
		clk, reset_n, onled, offled, valid : in std_logic;--clock(50), reset(key3), start led(key2), turn off led(key1), valid data input
		Led_rs,led_e,led_rw : out std_logic;--register select, enable, read/write
		data_out : out std_logic_vector(7 downto 0);--8bit bus to led
		r_data : in std_logic_vector(7 downto 0) --8bit bus who take charcater data from serial uart
	);
end component oled_ctrl;

begin

	s_uart : serial_uart
		port map(
			clk => clk50,
			reset => reset_n,
			rx => rx_in,
			received_error => ledr,
			received_valid => valid_int,
			received_data => data_int,
			tx => open,
			received_parity_error => open,
			transmit_ready => open,
			transmit_data => "00000000",
			transmit_valid => '0');

	s_oled : oled_ctrl
		port map(
			clk => clk50,
			reset_n => reset_n,
			onled => key2,
			offled => key1,
			r_data => data_int,
			valid => valid_int,

			data_out => open,
			led_rs => open,
			led_e => open,
			led_rw => open	);

end architecture str;