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a guest Dec 9th, 2018 75 Never
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  1. when S1C =>
  2.             Gate_MDR <= '1';
  3.             LD_IR <= '1';
  4.             LD_CC <= '1';
  5.             LD_ADDR1MUX <= '1';
  6.             MEM_EN <= '0';
  7.             next_state <= S2;
  8.            
  9. -------------------------------------
  10. ---- DECODE
  11. -------------------------------------  
  12.         when S2 =>
  13.         OPCODE := INPUT_IR(15 downto 12);
  14.         PC_OFFSET := INPUT_IR(8 downto 0);
  15.         DR := INPUT_IR(11 downto 9); --destination register
  16.         SR1 := INPUT_IR(8 downto 6); --source register 1
  17.         SR2 := INPUT_IR(2 downto 0); --source register 2
  18.             case OPCODE is
  19.             when LOAD =>
  20.                 LD_IR <= '0';
  21.                 Gate_MDR <= '0';
  22.                 LD_PC <= '0';
  23.                 Gate_PC <= '0';
  24.                 LD_ADDR2MUX <= "01";
  25.                 LD_MM <= '1';
  26.                 Gate_MARMUX <= '1';
  27.                 LD_MAR <= '1';
  28.                 next_state <= S5;
  29. when S5 =>
  30.             LD_MAR <= '1';
  31.             MEM_EN <= '1';
  32.             MEM_RW_EN <= '0';
  33.             Gate_MARMUX <= '0';
  34.             next_state <= S5A;
  35.         when S5A =>
  36.             LD_MAR <= '0';
  37.             LD_MDR <= '0';
  38.             Gate_MDR <= '1'; --put data on the bus
  39.             LD_DR <= DR;
  40.             LD_REG <= '1';
  41.             next_state <= S5B;
  42.         when S5B =>
  43.             Gate_MDR <= '0';
  44.             LD_REG <= '0';
  45.             next_state <= S1;
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