entity ula_4b is
    port
    (
        a, b    : in std_logic_vector(3 downto 0);
        x,y,z   : in std_logic;
        s       : out std_logic_vector(3 downto 0);
        co      : out std_logic
    );
end ula_4b;

architecture estrutural of ula_4b is

signal ia, ib, ci   : std_logic_vector(3 downto 0);

component sc_4b_ula port(
        x,y     : in std_logic_vector(3 downto 0);
        ei      : in std_logic_vector(3 downto 0);
        s       : out std_logic_vector(3 downto 0);
        zs      : out std_logic);
end component sc_4b_ula;

component ext port(
        a, b        : in std_logic_vector(3 downto 0);
        x,y,z       : in std_logic;
        ia,ib,cin   : out std_logic_vector(3 downto 0));
end component ext;

begin
    extensor: ext port map ( a, b, x, y, z , ia, ib, ci);
    scu: sc_4b_ula port map ( ia, ib, ci, s, co);
end estrutural;