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- mb M_AXI_DC, M_AXI_IC <-smart interconnect-> S_AXI_HP0
- mb M_AXI_DC <-smart interconnect 1-> S_AXI_HP0 zynq
- mb M_AXI_IC <-smart interconnect 2-> S_AXI_HP1 zynq
- mb M_AXI_DC S_AXI_HP0 zynq
- <-smart interconnect 1->
- mb M_AXI_IC S_AXI_HP1 zynq
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