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-- Company:
-- Engineer:
--
-- Create Date:    23:01:23 03/07/2019
-- Design Name:
-- Module Name:    lab6Top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lab6Top is
port (
    clk : in std_logic;
    op : in std_logic_vector(3 downto 0);
    reset : in std_logic;
    --button : in std_logic;
    digit_en : out std_logic_vector(3 downto 0);
    digit_out : out std_logic_vector(7 downto 0);
    SW : inout STD_LOGIC_VECTOR (1 downto 0);
    ALUOut : out std_logic_vector(15 downto 0);
    ALUIn1 : out std_logic_vector(15 downto 0);
    ALUIn2 : out std_logic_vector(15 downto 0);
    IMOut1 : out std_logic_vector(15 downto 0)
    );

end lab6Top;

architecture Behavioral of lab6Top is

component InstructionModule is
    port (
            clk : in std_logic;
            op : in std_logic_vector(3 downto 0);
            InstructionOut : out std_logic_vector(15 downto 0)
    );
end component;

component ALU is
generic (
Dwidth : integer := 16);
port (
        In1, In2 : in std_logic_vector(Dwidth - 1 downto 0);
        ALUout : out std_logic_vector(Dwidth - 1 downto 0);
        sel: in std_logic_vector (2 downto 0);
        Cin : in std_logic;
        zero, OVF, Cout : out std_logic
        );
end component;

component ControlUnit is
port (
    op : in STD_LOGIC_VECTOR (3 downto 0) := "0000";
    clk : in STD_LOGIC;
    reset : in STD_LOGIC;
--  button : in STD_LOGIC; --buton to go through different displays for an op code
    controlOut : out std_logic_vector(8 downto 0)
    );
end component;

component regfile is
  generic(
        Dwidth : integer := 16; --Data width (each register is 16 bits)
        Awidth : integer := 4); --Address Width (2^4 = 16 registers)
     Port (
        ReadA1, ReadA2, WriteA : in std_logic_vector(Awidth - 1 downto 0);
        DataD1, DataD2, Dummy : out std_logic_vector(Dwidth - 1 downto 0);
        DataIn : in std_logic_vector(Dwidth -1 downto 0);
        Wen, clk : in std_logic);
end component;

component sevenSeg is
    port ( microS : in  STD_LOGIC_VECTOR (15 downto 0);
           digit_out : out  STD_LOGIC_VECTOR (7 downto 0);
           digit_en : out  STD_LOGIC_VECTOR (3 downto 0);
              clk : in STD_LOGIC;
              SW : inout STD_LOGIC_VECTOR (1 downto 0)
              );
end component;

signal IMOut : std_logic_vector(15 downto 0);
signal RegtoALU1 : std_logic_vector(15 downto 0);
signal RegtoALU2 : std_logic_vector(15 downto 0);
signal DummySig : std_logic_vector(15 downto 0);
signal ALUOutSig : std_logic_vector(15 downto 0);
signal controlOutSig: std_logic_vector(8 downto 0);


signal ZeroSig : std_logic;
signal OVFSig : std_logic;
signal CoutSig : std_logic;
begin

IM: InstructionModule port map(clk, op, IMOut);
Control: ControlUnit port map(IMOut(15 downto 12), clk, reset, controlOutSig);
reg: regfile port map(IMOut(11 downto 8), IMOut(7 downto 4), IMOut(3 downto 0), RegtoALU1, RegtoALU2, DummySig, ALUOutSig, controlOutSig(5), clk);
ALU1: ALU port map(RegtoALU1, RegtoALU2, ALUOutSig, controlOutSig(4 downto 2), controlOutSig(1), ZeroSig, OVFSig, CoutSig);
seg: sevenSeg port map(ALUOutSig, digit_out, digit_en, clk, SW);

ALUOut <= ALUOutSig;
ALUIn1 <= RegtoALU1;
ALUIn2 <= RegtoALU2;
IMOut1 <= IMOut;
end Behavioral;