Counter

entity UPDOWN_COUNTER is

    Port(
        clk : int std_logic;  /* clock input*/
        reset : in std_logic; /*  reset input*/
        up_down : in std_logic /*  counting up or down*/
        counter : out std_logic_vector ( 3 downto 0)
    );

end UPDOWN_COUNTER

architecture Behavioral of UPDOWN_COUNTER is

    signal counter_updown: std_logic_vector ( 3 downto 0 );

    begin
        process(clk,reset)
            begin
                if ( reset = '1' ) then

                    counter_updown <= "0000";

                elsif (clk'event and clk = '1') then

                    if(up_down = '1') then

                        counter_updown <= counter_updown + 1;

                    else

                        counter_updown <= counter_updown - 1;

                    end if;

                end if;

        counter <= counter_updown;

        end process;


end Behavioral;