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  1. [smd@alaska openrisc]$ fusesoc --cores-root=/home/smd/work/coding/openrisc/mor1kx/ sim --sim=verilator  mor1kx-generic  --elf-load=/home/smd/work/coding/openrisc/dhrystone/dhrystone_10  --trace_enable > dhry_out
  2. ^C[smd@alaska openrisc]$ fusesoc --cores-root=/home/smd/work/coding/openrisc/mor1kx/ sim --sim=verilator  mor1kx-generic  --elf-load=/home/smd/work/coding/openrisc/dhrystone/dhrystone_10  --trace_enable
  3. WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in vlog_tb_utils
  4. WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in wb_intercon
  5. WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in wb_intercon-1.0
  6. WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in fifo-1.0
  7. WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in elf-loader
  8. WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in ram_wb
  9. WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in wb_sdram_ctrl
  10. WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in wb_altera_ddr_wrapper
  11. WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in stream_utils-1.0
  12. INFO:  Preparing verilator_tb_utils
  13. INFO:  Preparing adv_debug_sys
  14. INFO:  Preparing jtag_tap-1.13
  15. INFO:  Preparing mor1kx
  16. INFO:  Preparing uart16550-1.5.4
  17. INFO:  Preparing verilog-arbiter-r1
  18. INFO:  Preparing verilog_utils
  19. INFO:  Preparing wb_common
  20. INFO:  Preparing wb_intercon-1.0
  21. INFO:  Preparing wb_ram-1.0
  22. INFO:  Preparing elf-loader
  23. INFO:  Preparing mor1kx-generic
  24.  
  25. INFO:  Running /home/smd/work/coding/openrisc/orpsoc-cores/cores/elf-loader/check_libelf.sh
  26. /home/smd/work/coding/openrisc/build/mor1kx-generic/src/verilator_tb_utils/
  27. /home/smd/work/coding/openrisc/build/mor1kx-generic/src/elf-loader/
  28. /home/smd/work/coding/openrisc/build/mor1kx-generic/sim-verilator/bench/verilator
  29. /home/smd/work/coding/openrisc/build/mor1kx-generic/src
  30. INFO:  Verilating source
  31.  
  32. INFO:  Starting Verilator:
  33.  
  34. INFO:  Compiling verilator_tb_utils.cpp
  35. INFO:  Compiling jtagServer.cpp
  36. ar: creating verilator_tb_utils.a
  37. a - verilator_tb_utils.o
  38. a - jtagServer.o
  39.  
  40. INFO:  Compiling elf-loader.c
  41. ar: creating elf-loader.a
  42. a - elf-loader.o
  43.  
  44. INFO:  Building verilator executable:
  45. /home/smd/work/coding/openrisc/build/mor1kx-generic/src/mor1kx-generic/bench/verilator/tb.cpp: In function ‘int main(int, char**, char**)’:
  46. /home/smd/work/coding/openrisc/build/mor1kx-generic/src/mor1kx-generic/bench/verilator/tb.cpp:89:29: error: ‘class Vorpsoc_top’ has no member named ‘v’
  47.    new VerilatorTbUtils(top->v->wb_bfm_memory0->ram0->mem);
  48.                              ^
  49. /home/smd/work/coding/openrisc/build/mor1kx-generic/src/mor1kx-generic/bench/verilator/tb.cpp:110:15: error: ‘class Vorpsoc_top’ has no member named ‘v’
  50.    insn = top->v->mor1kx0->mor1kx_cpu->monitor_execute_insn;
  51.                ^
  52. /home/smd/work/coding/openrisc/build/mor1kx-generic/src/mor1kx-generic/bench/verilator/tb.cpp:111:16: error: ‘class Vorpsoc_top’ has no member named ‘v’
  53.    ex_pc = top->v->mor1kx0->mor1kx_cpu->monitor_execute_pc;
  54.                 ^
  55. At global scope:
  56. cc1plus: warning: unrecognized command line option ‘-Wno-parentheses-equality’
  57. make: *** [tb.o] Error 1
  58. ERROR: Failed to build simulation model
  59. ERROR: "make -f Vorpsoc_top.mk Vorpsoc_top" exited with an error code.
  60. ERROR: See stderr for details.
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