test2

library IEEE; use IEEE.STD_LOGIC_1164.all;
entity seven_seg_decoder is
 port(data: in STD_LOGIC_VECTOR(7 downto 0);
 segments: out STD_LOGIC_VECTOR(9 downto 0));
end;
architecture synth of seven_seg_decoder is
begin
 process(all) begin
 case data is
 when"00000001" => segments <= "1000000000",
 when"00000010" => segments <= "0100000000",
 when"00000011" => segments <= "0010000000",
 when"00000100" => segments <= "0001000000",
 when"00000101" => segments <= "0000100000",
 when"00000110" => segments <= "0000010000",
 when"00000111" => segments <= "0000001000",
 when"00001000" => segments <= "0000000100",
 when"00001001" => segments <= "0000000010",
 when"00001010" => segments <= "0000000001",
 when others => segments <= "0000000000";
 end case;
 end process;
end;