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ebnoemuslim
Jan 26th, 2023
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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x01>;
  5. #size-cells = <0x01>;
  6. model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
  7. compatible = "qcom,ipq40xx-apdk01.1\0qcom,ipq40xx";
  8. interrupt-parent = <0x01>;
  9.  
  10. chosen {
  11. bootargs-append = " clk_ignore_unused";
  12. };
  13.  
  14. aliases {
  15. spi0 = "/soc/spi@78b5000";
  16. i2c0 = "/soc/i2c@78b7000";
  17. ethernet0 = "/soc/edma/gmac0";
  18. ethernet1 = "/soc/edma/gmac1";
  19. };
  20.  
  21. memory {
  22. device_type = "memory";
  23. reg = <0x80000000 0x10000000>;
  24. };
  25.  
  26. cpus {
  27. #address-cells = <0x01>;
  28. #size-cells = <0x00>;
  29.  
  30. cpu@0 {
  31. device_type = "cpu";
  32. compatible = "arm,cortex-a7";
  33. enable-method = "qcom,arm-cortex-acc";
  34. reg = <0x00>;
  35. clocks = <0x02 0x09>;
  36. clock-frequency = <0x00>;
  37. };
  38.  
  39. cpu@1 {
  40. device_type = "cpu";
  41. compatible = "arm,cortex-a7";
  42. enable-method = "qcom,arm-cortex-acc";
  43. reg = <0x01>;
  44. clocks = <0x02 0x09>;
  45. clock-frequency = <0x00>;
  46. };
  47.  
  48. cpu@2 {
  49. device_type = "cpu";
  50. compatible = "arm,cortex-a7";
  51. enable-method = "qcom,arm-cortex-acc";
  52. reg = <0x02>;
  53. clocks = <0x02 0x09>;
  54. clock-frequency = <0x00>;
  55. };
  56.  
  57. cpu@3 {
  58. device_type = "cpu";
  59. compatible = "arm,cortex-a7";
  60. enable-method = "qcom,arm-cortex-acc";
  61. reg = <0x03>;
  62. clocks = <0x02 0x09>;
  63. clock-frequency = <0x00>;
  64. };
  65. };
  66.  
  67. clocks {
  68.  
  69. gcc_sleep_clk_src {
  70. compatible = "fixed-clock";
  71. clock-frequency = <0x7d00>;
  72. #clock-cells = <0x00>;
  73. linux,phandle = <0x47>;
  74. phandle = <0x47>;
  75. };
  76.  
  77. xo {
  78. compatible = "fixed-clock";
  79. clock-frequency = <0x2dc6c00>;
  80. #clock-cells = <0x00>;
  81. };
  82. };
  83.  
  84. soc {
  85. #address-cells = <0x01>;
  86. #size-cells = <0x01>;
  87. ranges;
  88. compatible = "simple-bus";
  89.  
  90. ad-hoc-bus {
  91. compatible = "qcom,msm-bus-device";
  92. reg = <0x580000 0x14000 0x500000 0x11000>;
  93. reg-names = "snoc-base\0pcnoc-base";
  94.  
  95. fab-pcnoc {
  96. cell-id = <0x1000>;
  97. label = "fab-pcnoc";
  98. qcom,fab-dev;
  99. qcom,base-name = "pcnoc-base";
  100. qcom,bypass-qos-prg;
  101. qcom,bus-type = <0x01>;
  102. qcom,qos-off = <0x1000>;
  103. qcom,base-offset = <0x00>;
  104. clocks;
  105. linux,phandle = <0x04>;
  106. phandle = <0x04>;
  107. };
  108.  
  109. fab-snoc {
  110. cell-id = <0x400>;
  111. label = "fab-snoc";
  112. qcom,fab-dev;
  113. qcom,base-name = "snoc-base";
  114. qcom,bypass-qos-prg;
  115. qcom,bus-type = <0x01>;
  116. qcom,qos-off = <0x80>;
  117. qcom,base-offset = <0x00>;
  118. clocks;
  119. linux,phandle = <0x31>;
  120. phandle = <0x31>;
  121. };
  122.  
  123. mas-blsp-bam {
  124. cell-id = <0x6d>;
  125. label = "mas-blsp-bam";
  126. qcom,buswidth = <0x04>;
  127. qcom,ap-owned;
  128. qcom,connections = <0x03>;
  129. qcom,bus-dev = <0x04>;
  130. qcom,mas-rpm-id = <0x82>;
  131. qcom,blacklist = <0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a>;
  132. };
  133.  
  134. mas-usb2-bam {
  135. cell-id = <0x6e>;
  136. label = "mas-usb2-bam";
  137. qcom,buswidth = <0x08>;
  138. qcom,ap-owned;
  139. qcom,qport = <0x0f>;
  140. qcom,qos-mode = "fixed";
  141. qcom,connections = <0x2b>;
  142. qcom,prio1 = <0x01>;
  143. qcom,prio0 = <0x01>;
  144. qcom,bus-dev = <0x04>;
  145. qcom,mas-rpm-id = <0x83>;
  146. qcom,blacklist = <0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a>;
  147. };
  148.  
  149. mas-adss-dma0 {
  150. cell-id = <0x6f>;
  151. label = "mas-adss-dma0";
  152. qcom,buswidth = <0x04>;
  153. qcom,ap-owned;
  154. qcom,connections = <0x2c>;
  155. qcom,bus-dev = <0x04>;
  156. qcom,mas-rpm-id = <0x84>;
  157. qcom,blacklist = <0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a>;
  158. };
  159.  
  160. mas-adss-dma1 {
  161. cell-id = <0x70>;
  162. label = "mas-adss-dma1";
  163. qcom,buswidth = <0x04>;
  164. qcom,ap-owned;
  165. qcom,connections = <0x2c>;
  166. qcom,bus-dev = <0x04>;
  167. qcom,mas-rpm-id = <0x85>;
  168. qcom,blacklist = <0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a>;
  169. };
  170.  
  171. mas-adss-dma2 {
  172. cell-id = <0x71>;
  173. label = "mas-adss-dma2";
  174. qcom,buswidth = <0x04>;
  175. qcom,ap-owned;
  176. qcom,connections = <0x2c>;
  177. qcom,bus-dev = <0x04>;
  178. qcom,mas-rpm-id = <0x86>;
  179. qcom,blacklist = <0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a>;
  180. };
  181.  
  182. mas-adss-dma3 {
  183. cell-id = <0x72>;
  184. label = "mas-adss-dma3";
  185. qcom,buswidth = <0x04>;
  186. qcom,ap-owned;
  187. qcom,connections = <0x2c>;
  188. qcom,bus-dev = <0x04>;
  189. qcom,mas-rpm-id = <0x87>;
  190. qcom,blacklist = <0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a>;
  191. };
  192.  
  193. mas-qpic-bam {
  194. cell-id = <0x73>;
  195. label = "mas-qpic-bam";
  196. qcom,buswidth = <0x04>;
  197. qcom,ap-owned;
  198. qcom,connections = <0x03>;
  199. qcom,bus-dev = <0x04>;
  200. qcom,mas-rpm-id = <0x88>;
  201. qcom,blacklist = <0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a>;
  202. };
  203.  
  204. mas-spdm {
  205. cell-id = <0x24>;
  206. label = "mas-spdm";
  207. qcom,buswidth = <0x04>;
  208. qcom,ap-owned;
  209. qcom,connections = <0x03>;
  210. qcom,bus-dev = <0x04>;
  211. qcom,mas-rpm-id = <0x32>;
  212. qcom,blacklist = <0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a>;
  213. };
  214.  
  215. mas-pcnoc-cfg {
  216. cell-id = <0x58>;
  217. label = "mas-pcnoc-cfg";
  218. qcom,buswidth = <0x04>;
  219. qcom,ap-owned;
  220. qcom,connections = <0x26>;
  221. qcom,bus-dev = <0x04>;
  222. qcom,mas-rpm-id = <0x54>;
  223. };
  224.  
  225. mas-tic {
  226. cell-id = <0x4d>;
  227. label = "mas-tic";
  228. qcom,buswidth = <0x04>;
  229. qcom,ap-owned;
  230. qcom,connections = <0x2d 0x2b>;
  231. qcom,bus-dev = <0x04>;
  232. qcom,mas-rpm-id = <0x33>;
  233. };
  234.  
  235. mas-sdcc-bam {
  236. cell-id = <0x74>;
  237. label = "mas-sdcc-bam";
  238. qcom,buswidth = <0x08>;
  239. qcom,ap-owned;
  240. qcom,qport = <0x0e>;
  241. qcom,qos-mode = "fixed";
  242. qcom,connections = <0x2b>;
  243. qcom,prio1 = <0x00>;
  244. qcom,prio0 = <0x00>;
  245. qcom,bus-dev = <0x04>;
  246. qcom,mas-rpm-id = <0x89>;
  247. qcom,blacklist = <0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a>;
  248. };
  249.  
  250. mas-snoc-pcnoc {
  251. cell-id = <0x2739>;
  252. label = "mas-snoc-pcnoc";
  253. qcom,buswidth = <0x04>;
  254. qcom,ap-owned;
  255. qcom,qport = <0x10>;
  256. qcom,qos-mode = "fixed";
  257. qcom,connections = <0x2d>;
  258. qcom,prio1 = <0x00>;
  259. qcom,prio0 = <0x00>;
  260. qcom,bus-dev = <0x04>;
  261. qcom,mas-rpm-id = <0x4d>;
  262. };
  263.  
  264. mas-qdss-dap {
  265. cell-id = <0x4c>;
  266. label = "mas-qdss-dap";
  267. qcom,buswidth = <0x04>;
  268. qcom,ap-owned;
  269. qcom,connections = <0x2d 0x2b>;
  270. qcom,bus-dev = <0x04>;
  271. qcom,mas-rpm-id = <0x31>;
  272. };
  273.  
  274. mas-ddrc-snoc {
  275. cell-id = <0x75>;
  276. label = "mas-ddrc-snoc";
  277. qcom,buswidth = <0x10>;
  278. qcom,ap-owned;
  279. qcom,connections = <0x2e 0x2f 0x30>;
  280. qcom,bus-dev = <0x31>;
  281. qcom,mas-rpm-id = <0x8a>;
  282. qcom,blacklist = <0x32 0x33>;
  283. };
  284.  
  285. mas-wss-0 {
  286. cell-id = <0x76>;
  287. label = "mas-wss-0";
  288. qcom,buswidth = <0x04>;
  289. qcom,ap-owned;
  290. qcom,qport = <0x1a>;
  291. qcom,qos-mode = "fixed";
  292. qcom,connections = <0x2e 0x32>;
  293. qcom,prio1 = <0x00>;
  294. qcom,prio0 = <0x00>;
  295. qcom,bus-dev = <0x31>;
  296. qcom,mas-rpm-id = <0x8b>;
  297. qcom,blacklist = <0x34 0x35 0x30 0x36 0x37 0x38 0x33>;
  298. };
  299.  
  300. mas-wss-1 {
  301. cell-id = <0x77>;
  302. label = "mas-wss-1";
  303. qcom,buswidth = <0x04>;
  304. qcom,ap-owned;
  305. qcom,qport = <0x1b>;
  306. qcom,qos-mode = "fixed";
  307. qcom,connections = <0x2e 0x32>;
  308. qcom,prio1 = <0x00>;
  309. qcom,prio0 = <0x00>;
  310. qcom,bus-dev = <0x31>;
  311. qcom,mas-rpm-id = <0x8c>;
  312. qcom,blacklist = <0x34 0x35 0x30 0x36 0x37 0x38 0x33>;
  313. };
  314.  
  315. mas-crypto {
  316. cell-id = <0x2f>;
  317. label = "mas-crypto";
  318. qcom,buswidth = <0x08>;
  319. qcom,ap-owned;
  320. qcom,qport = <0x05>;
  321. qcom,qos-mode = "fixed";
  322. qcom,connections = <0x2e 0x2f 0x32>;
  323. qcom,prio1 = <0x00>;
  324. qcom,prio0 = <0x00>;
  325. qcom,bus-dev = <0x31>;
  326. qcom,mas-rpm-id = <0x17>;
  327. qcom,blacklist = <0x34 0x35 0x39 0x30 0x3a 0x38 0x33>;
  328. };
  329.  
  330. mas-ess {
  331. cell-id = <0x78>;
  332. label = "mas-ess";
  333. qcom,buswidth = <0x08>;
  334. qcom,ap-owned;
  335. qcom,qport = <0x2c>;
  336. qcom,qos-mode = "fixed";
  337. qcom,connections = <0x2e 0x32>;
  338. qcom,prio1 = <0x00>;
  339. qcom,prio0 = <0x00>;
  340. qcom,bus-dev = <0x31>;
  341. qcom,mas-rpm-id = <0x8d>;
  342. qcom,blacklist = <0x34 0x35 0x39 0x30 0x3a 0x36 0x37 0x38 0x33>;
  343. };
  344.  
  345. mas-pcie {
  346. cell-id = <0x2d>;
  347. label = "mas-pcie";
  348. qcom,buswidth = <0x08>;
  349. qcom,ap-owned;
  350. qcom,qport = <0x06>;
  351. qcom,qos-mode = "fixed";
  352. qcom,connections = <0x2e 0x32>;
  353. qcom,prio1 = <0x00>;
  354. qcom,prio0 = <0x00>;
  355. qcom,bus-dev = <0x31>;
  356. qcom,mas-rpm-id = <0x8e>;
  357. qcom,blacklist = <0x34 0x35 0x30 0x3a 0x36 0x37 0x38 0x33>;
  358. };
  359.  
  360. mas-usb3 {
  361. cell-id = <0x3d>;
  362. label = "mas-usb3";
  363. qcom,buswidth = <0x08>;
  364. qcom,ap-owned;
  365. qcom,qport = <0x07>;
  366. qcom,qos-mode = "fixed";
  367. qcom,connections = <0x2e 0x32>;
  368. qcom,prio1 = <0x00>;
  369. qcom,prio0 = <0x00>;
  370. qcom,bus-dev = <0x31>;
  371. qcom,mas-rpm-id = <0x20>;
  372. qcom,blacklist = <0x34 0x35 0x39 0x30 0x3a 0x36 0x37 0x38 0x33>;
  373. };
  374.  
  375. mas-qdss-etr {
  376. cell-id = <0x3c>;
  377. label = "mas-qdss-etr";
  378. qcom,buswidth = <0x08>;
  379. qcom,ap-owned;
  380. qcom,qport = <0x220>;
  381. qcom,qos-mode = "fixed";
  382. qcom,connections = <0x3b>;
  383. qcom,prio1 = <0x00>;
  384. qcom,prio0 = <0x00>;
  385. qcom,bus-dev = <0x31>;
  386. qcom,mas-rpm-id = <0x1f>;
  387. qcom,blacklist = <0x34 0x35 0x39 0x30 0x3a 0x36 0x37 0x38 0x33>;
  388. };
  389.  
  390. mas-qdss-bamndp {
  391. cell-id = <0x79>;
  392. label = "mas-qdss-bamndp";
  393. qcom,buswidth = <0x04>;
  394. qcom,ap-owned;
  395. qcom,qport = <0x240>;
  396. qcom,qos-mode = "fixed";
  397. qcom,connections = <0x3b>;
  398. qcom,prio1 = <0x00>;
  399. qcom,prio0 = <0x00>;
  400. qcom,bus-dev = <0x31>;
  401. qcom,mas-rpm-id = <0x8f>;
  402. qcom,blacklist = <0x34 0x35 0x39 0x30 0x3a 0x36 0x37 0x38 0x33>;
  403. };
  404.  
  405. mas-pcnoc-snoc {
  406. cell-id = <0x271a>;
  407. label = "mas-pcnoc-snoc";
  408. qcom,buswidth = <0x04>;
  409. qcom,ap-owned;
  410. qcom,qport = <0x180>;
  411. qcom,qos-mode = "fixed";
  412. qcom,connections = <0x2e 0x2f 0x32>;
  413. qcom,prio1 = <0x00>;
  414. qcom,prio0 = <0x00>;
  415. qcom,bus-dev = <0x31>;
  416. qcom,mas-rpm-id = <0x1d>;
  417. qcom,blacklist = <0x33>;
  418. };
  419.  
  420. mas-snoc-cfg {
  421. cell-id = <0x7a>;
  422. label = "mas-snoc-cfg";
  423. qcom,buswidth = <0x04>;
  424. qcom,ap-owned;
  425. qcom,connections = <0x33>;
  426. qcom,bus-dev = <0x31>;
  427. qcom,mas-rpm-id = <0x90>;
  428. };
  429.  
  430. pcnoc-m-0 {
  431. cell-id = <0x271e>;
  432. label = "pcnoc-m-0";
  433. qcom,buswidth = <0x04>;
  434. qcom,ap-owned;
  435. qcom,qport = <0x0c>;
  436. qcom,qos-mode = "fixed";
  437. qcom,connections = <0x2b>;
  438. qcom,prio1 = <0x01>;
  439. qcom,prio0 = <0x01>;
  440. qcom,bus-dev = <0x04>;
  441. qcom,mas-rpm-id = <0x57>;
  442. qcom,slv-rpm-id = <0x74>;
  443. linux,phandle = <0x03>;
  444. phandle = <0x03>;
  445. };
  446.  
  447. pcnoc-m-1 {
  448. cell-id = <0x271f>;
  449. label = "pcnoc-m-1";
  450. qcom,buswidth = <0x04>;
  451. qcom,ap-owned;
  452. qcom,qport = <0x0d>;
  453. qcom,qos-mode = "fixed";
  454. qcom,connections = <0x2b>;
  455. qcom,prio1 = <0x01>;
  456. qcom,prio0 = <0x01>;
  457. qcom,bus-dev = <0x04>;
  458. qcom,mas-rpm-id = <0x58>;
  459. qcom,slv-rpm-id = <0x75>;
  460. linux,phandle = <0x2c>;
  461. phandle = <0x2c>;
  462. };
  463.  
  464. pcnoc-int-0 {
  465. cell-id = <0x271c>;
  466. label = "pcnoc-int-0";
  467. qcom,buswidth = <0x08>;
  468. qcom,ap-owned;
  469. qcom,connections = <0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45>;
  470. qcom,bus-dev = <0x04>;
  471. qcom,mas-rpm-id = <0x55>;
  472. qcom,slv-rpm-id = <0x72>;
  473. linux,phandle = <0x2d>;
  474. phandle = <0x2d>;
  475. };
  476.  
  477. pcnoc-s-0 {
  478. cell-id = <0x2722>;
  479. label = "pcnoc-s-0";
  480. qcom,buswidth = <0x04>;
  481. qcom,ap-owned;
  482. qcom,connections = <0x22 0x05 0x1b 0x17>;
  483. qcom,bus-dev = <0x04>;
  484. qcom,mas-rpm-id = <0x59>;
  485. qcom,slv-rpm-id = <0x76>;
  486. linux,phandle = <0x3e>;
  487. phandle = <0x3e>;
  488. };
  489.  
  490. pcnoc-s-1 {
  491. cell-id = <0x2723>;
  492. label = "pcnoc-s-1";
  493. qcom,buswidth = <0x04>;
  494. qcom,ap-owned;
  495. qcom,connections = <0x19 0x12 0x10>;
  496. qcom,bus-dev = <0x04>;
  497. qcom,mas-rpm-id = <0x5a>;
  498. qcom,slv-rpm-id = <0x77>;
  499. linux,phandle = <0x3c>;
  500. phandle = <0x3c>;
  501. };
  502.  
  503. pcnoc-s-2 {
  504. cell-id = <0x2724>;
  505. label = "pcnoc-s-2";
  506. qcom,buswidth = <0x04>;
  507. qcom,ap-owned;
  508. qcom,connections = <0x1c 0x1d 0x0e 0x1a>;
  509. qcom,bus-dev = <0x04>;
  510. qcom,mas-rpm-id = <0x5b>;
  511. qcom,slv-rpm-id = <0x78>;
  512. linux,phandle = <0x3d>;
  513. phandle = <0x3d>;
  514. };
  515.  
  516. pcnoc-s-3 {
  517. cell-id = <0x2725>;
  518. label = "pcnoc-s-3";
  519. qcom,buswidth = <0x04>;
  520. qcom,ap-owned;
  521. qcom,connections = <0x13 0x16 0x2a 0x27>;
  522. qcom,bus-dev = <0x04>;
  523. qcom,mas-rpm-id = <0x5c>;
  524. qcom,slv-rpm-id = <0x79>;
  525. linux,phandle = <0x45>;
  526. phandle = <0x45>;
  527. };
  528.  
  529. pcnoc-s-4 {
  530. cell-id = <0x2726>;
  531. label = "pcnoc-s-4";
  532. qcom,buswidth = <0x04>;
  533. qcom,ap-owned;
  534. qcom,connections = <0x07 0x21 0x23>;
  535. qcom,bus-dev = <0x04>;
  536. qcom,mas-rpm-id = <0x5d>;
  537. qcom,slv-rpm-id = <0x7a>;
  538. linux,phandle = <0x3f>;
  539. phandle = <0x3f>;
  540. };
  541.  
  542. pcnoc-s-5 {
  543. cell-id = <0x273f>;
  544. label = "pcnoc-s-5";
  545. qcom,buswidth = <0x04>;
  546. qcom,ap-owned;
  547. qcom,connections = <0x20 0x08 0x06 0x11>;
  548. qcom,bus-dev = <0x04>;
  549. qcom,mas-rpm-id = <0x81>;
  550. qcom,slv-rpm-id = <0xbd>;
  551. linux,phandle = <0x40>;
  552. phandle = <0x40>;
  553. };
  554.  
  555. pcnoc-s-6 {
  556. cell-id = <0x2740>;
  557. label = "pcnoc-s-6";
  558. qcom,buswidth = <0x04>;
  559. qcom,ap-owned;
  560. qcom,connections = <0x0b 0x15 0x1e 0x0d 0x0a>;
  561. qcom,bus-dev = <0x04>;
  562. qcom,mas-rpm-id = <0x5e>;
  563. qcom,slv-rpm-id = <0x7b>;
  564. linux,phandle = <0x41>;
  565. phandle = <0x41>;
  566. };
  567.  
  568. pcnoc-s-7 {
  569. cell-id = <0x2752>;
  570. label = "pcnoc-s-7";
  571. qcom,buswidth = <0x04>;
  572. qcom,ap-owned;
  573. qcom,connections = <0x0f 0x25 0x1f>;
  574. qcom,bus-dev = <0x04>;
  575. qcom,mas-rpm-id = <0x5f>;
  576. qcom,slv-rpm-id = <0x7c>;
  577. linux,phandle = <0x42>;
  578. phandle = <0x42>;
  579. };
  580.  
  581. pcnoc-s-8 {
  582. cell-id = <0x2727>;
  583. label = "pcnoc-s-8";
  584. qcom,buswidth = <0x04>;
  585. qcom,ap-owned;
  586. qcom,connections = <0x29 0x0c 0x24>;
  587. qcom,bus-dev = <0x04>;
  588. qcom,mas-rpm-id = <0x60>;
  589. qcom,slv-rpm-id = <0x7d>;
  590. linux,phandle = <0x43>;
  591. phandle = <0x43>;
  592. };
  593.  
  594. pcnoc-s-9 {
  595. cell-id = <0x2728>;
  596. label = "pcnoc-s-9";
  597. qcom,buswidth = <0x04>;
  598. qcom,ap-owned;
  599. qcom,connections = <0x09 0x28 0x18 0x14>;
  600. qcom,bus-dev = <0x04>;
  601. qcom,mas-rpm-id = <0x61>;
  602. qcom,slv-rpm-id = <0x7e>;
  603. linux,phandle = <0x44>;
  604. phandle = <0x44>;
  605. };
  606.  
  607. snoc-int-0 {
  608. cell-id = <0x2714>;
  609. label = "snoc-int-0";
  610. qcom,buswidth = <0x08>;
  611. qcom,ap-owned;
  612. qcom,connections = <0x46 0x3a>;
  613. qcom,bus-dev = <0x31>;
  614. qcom,mas-rpm-id = <0x63>;
  615. qcom,slv-rpm-id = <0x82>;
  616. linux,phandle = <0x2e>;
  617. phandle = <0x2e>;
  618. };
  619.  
  620. snoc-int-1 {
  621. cell-id = <0x2715>;
  622. label = "snoc-int-1";
  623. qcom,buswidth = <0x08>;
  624. qcom,ap-owned;
  625. qcom,connections = <0x38 0x39 0x35 0x34 0x36 0x37>;
  626. qcom,bus-dev = <0x31>;
  627. qcom,mas-rpm-id = <0x64>;
  628. qcom,slv-rpm-id = <0x83>;
  629. linux,phandle = <0x2f>;
  630. phandle = <0x2f>;
  631. };
  632.  
  633. qdss-int {
  634. cell-id = <0x2719>;
  635. label = "qdss-int";
  636. qcom,buswidth = <0x08>;
  637. qcom,ap-owned;
  638. qcom,connections = <0x2e 0x32>;
  639. qcom,bus-dev = <0x31>;
  640. qcom,mas-rpm-id = <0x62>;
  641. qcom,slv-rpm-id = <0x80>;
  642. linux,phandle = <0x3b>;
  643. phandle = <0x3b>;
  644. };
  645.  
  646. slv-clk-ctl {
  647. cell-id = <0x26c>;
  648. label = "slv-clk-ctl";
  649. qcom,buswidth = <0x04>;
  650. qcom,ap-owned;
  651. qcom,bus-dev = <0x04>;
  652. qcom,slv-rpm-id = <0x2f>;
  653. linux,phandle = <0x22>;
  654. phandle = <0x22>;
  655. };
  656.  
  657. slv-security {
  658. cell-id = <0x26e>;
  659. label = "slv-security";
  660. qcom,buswidth = <0x04>;
  661. qcom,ap-owned;
  662. qcom,bus-dev = <0x04>;
  663. qcom,slv-rpm-id = <0x31>;
  664. linux,phandle = <0x1b>;
  665. phandle = <0x1b>;
  666. };
  667.  
  668. slv-tcsr {
  669. cell-id = <0x26f>;
  670. label = "slv-tcsr";
  671. qcom,buswidth = <0x04>;
  672. qcom,ap-owned;
  673. qcom,bus-dev = <0x04>;
  674. qcom,slv-rpm-id = <0x32>;
  675. linux,phandle = <0x05>;
  676. phandle = <0x05>;
  677. };
  678.  
  679. slv-tlmm {
  680. cell-id = <0x270>;
  681. label = "slv-tlmm";
  682. qcom,buswidth = <0x04>;
  683. qcom,ap-owned;
  684. qcom,bus-dev = <0x04>;
  685. qcom,slv-rpm-id = <0x33>;
  686. linux,phandle = <0x17>;
  687. phandle = <0x17>;
  688. };
  689.  
  690. slv-imem-cfg {
  691. cell-id = <0x273>;
  692. label = "slv-imem-cfg";
  693. qcom,buswidth = <0x04>;
  694. qcom,ap-owned;
  695. qcom,bus-dev = <0x04>;
  696. qcom,slv-rpm-id = <0x36>;
  697. linux,phandle = <0x10>;
  698. phandle = <0x10>;
  699. };
  700.  
  701. slv-prng {
  702. cell-id = <0x26a>;
  703. label = "slv-prng";
  704. qcom,buswidth = <0x04>;
  705. qcom,ap-owned;
  706. qcom,bus-dev = <0x04>;
  707. qcom,slv-rpm-id = <0x2c>;
  708. linux,phandle = <0x12>;
  709. phandle = <0x12>;
  710. };
  711.  
  712. slv-prng-apu-cfg {
  713. cell-id = <0x2cc>;
  714. label = "slv-prng-apu-cfg";
  715. qcom,buswidth = <0x04>;
  716. qcom,ap-owned;
  717. qcom,bus-dev = <0x04>;
  718. qcom,slv-rpm-id = <0xbe>;
  719. linux,phandle = <0x19>;
  720. phandle = <0x19>;
  721. };
  722.  
  723. slv-boot-rom {
  724. cell-id = <0x276>;
  725. label = "slv-boot-rom";
  726. qcom,buswidth = <0x04>;
  727. qcom,ap-owned;
  728. qcom,bus-dev = <0x04>;
  729. qcom,slv-rpm-id = <0x39>;
  730. linux,phandle = <0x1a>;
  731. phandle = <0x1a>;
  732. };
  733.  
  734. slv-spdm {
  735. cell-id = <0x279>;
  736. label = "slv-spdm";
  737. qcom,buswidth = <0x04>;
  738. qcom,ap-owned;
  739. qcom,bus-dev = <0x04>;
  740. qcom,slv-rpm-id = <0x3c>;
  741. linux,phandle = <0x1c>;
  742. phandle = <0x1c>;
  743. };
  744.  
  745. slv-pcnoc-cfg {
  746. cell-id = <0x281>;
  747. label = "slv-pcnoc-cfg";
  748. qcom,buswidth = <0x04>;
  749. qcom,ap-owned;
  750. qcom,bus-dev = <0x04>;
  751. qcom,slv-rpm-id = <0x45>;
  752. linux,phandle = <0x0e>;
  753. phandle = <0x0e>;
  754. };
  755.  
  756. slv-pcnoc-mpu-cfg {
  757. cell-id = <0x2cd>;
  758. label = "slv-pcnoc-mpu-cfg";
  759. qcom,buswidth = <0x04>;
  760. qcom,ap-owned;
  761. qcom,bus-dev = <0x04>;
  762. qcom,slv-rpm-id = <0xbf>;
  763. linux,phandle = <0x1d>;
  764. phandle = <0x1d>;
  765. };
  766.  
  767. slv-gcnt {
  768. cell-id = <0x2ce>;
  769. label = "slv-gcnt";
  770. qcom,buswidth = <0x04>;
  771. qcom,ap-owned;
  772. qcom,bus-dev = <0x04>;
  773. qcom,slv-rpm-id = <0xc0>;
  774. linux,phandle = <0x16>;
  775. phandle = <0x16>;
  776. };
  777.  
  778. slv-qdss-cfg {
  779. cell-id = <0x27b>;
  780. label = "slv-qdss-cfg";
  781. qcom,buswidth = <0x04>;
  782. qcom,ap-owned;
  783. qcom,bus-dev = <0x04>;
  784. qcom,slv-rpm-id = <0x3f>;
  785. linux,phandle = <0x13>;
  786. phandle = <0x13>;
  787. };
  788.  
  789. slv-snoc-cfg {
  790. cell-id = <0x282>;
  791. label = "slv-snoc-cfg";
  792. qcom,buswidth = <0x04>;
  793. qcom,ap-owned;
  794. qcom,bus-dev = <0x04>;
  795. qcom,slv-rpm-id = <0x46>;
  796. linux,phandle = <0x2a>;
  797. phandle = <0x2a>;
  798. };
  799.  
  800. slv-snoc-mpu-cfg {
  801. cell-id = <0x27e>;
  802. label = "slv-snoc-mpu-cfg";
  803. qcom,buswidth = <0x04>;
  804. qcom,ap-owned;
  805. qcom,bus-dev = <0x04>;
  806. qcom,slv-rpm-id = <0x43>;
  807. linux,phandle = <0x27>;
  808. phandle = <0x27>;
  809. };
  810.  
  811. slv-adss-cfg {
  812. cell-id = <0x2cf>;
  813. label = "slv-adss-cfg";
  814. qcom,buswidth = <0x04>;
  815. qcom,ap-owned;
  816. qcom,bus-dev = <0x04>;
  817. qcom,slv-rpm-id = <0xc1>;
  818. linux,phandle = <0x07>;
  819. phandle = <0x07>;
  820. };
  821.  
  822. slv-adss-apu {
  823. cell-id = <0x2d0>;
  824. label = "slv-adss-apu";
  825. qcom,buswidth = <0x04>;
  826. qcom,ap-owned;
  827. qcom,bus-dev = <0x04>;
  828. qcom,slv-rpm-id = <0xc2>;
  829. linux,phandle = <0x23>;
  830. phandle = <0x23>;
  831. };
  832.  
  833. slv-adss-vmidmt-cfg {
  834. cell-id = <0x2d0>;
  835. label = "slv-adss-vmidmt-cfg";
  836. qcom,buswidth = <0x04>;
  837. qcom,ap-owned;
  838. qcom,bus-dev = <0x04>;
  839. qcom,slv-rpm-id = <0xc3>;
  840. linux,phandle = <0x21>;
  841. phandle = <0x21>;
  842. };
  843.  
  844. slv-qhss-apu-cfg {
  845. cell-id = <0x2d1>;
  846. label = "slv-qhss-apu-cfg";
  847. qcom,buswidth = <0x04>;
  848. qcom,ap-owned;
  849. qcom,bus-dev = <0x04>;
  850. qcom,slv-rpm-id = <0xc4>;
  851. linux,phandle = <0x20>;
  852. phandle = <0x20>;
  853. };
  854.  
  855. slv-mdio {
  856. cell-id = <0x2d2>;
  857. label = "slv-mdio";
  858. qcom,buswidth = <0x04>;
  859. qcom,ap-owned;
  860. qcom,bus-dev = <0x04>;
  861. qcom,slv-rpm-id = <0xc5>;
  862. linux,phandle = <0x06>;
  863. phandle = <0x06>;
  864. };
  865.  
  866. slv-fephy-cfg {
  867. cell-id = <0x2d3>;
  868. label = "slv-fephy-cfg";
  869. qcom,buswidth = <0x04>;
  870. qcom,ap-owned;
  871. qcom,bus-dev = <0x04>;
  872. qcom,slv-rpm-id = <0xc6>;
  873. linux,phandle = <0x08>;
  874. phandle = <0x08>;
  875. };
  876.  
  877. slv-srif {
  878. cell-id = <0x2d4>;
  879. label = "slv-srif";
  880. qcom,buswidth = <0x04>;
  881. qcom,ap-owned;
  882. qcom,bus-dev = <0x04>;
  883. qcom,slv-rpm-id = <0xc7>;
  884. linux,phandle = <0x11>;
  885. phandle = <0x11>;
  886. };
  887.  
  888. slv-ddrc-cfg {
  889. cell-id = <0x2db>;
  890. label = "slv-ddrc-cfg";
  891. qcom,buswidth = <0x04>;
  892. qcom,ap-owned;
  893. qcom,bus-dev = <0x04>;
  894. qcom,slv-rpm-id = <0xc8>;
  895. linux,phandle = <0x0d>;
  896. phandle = <0x0d>;
  897. };
  898.  
  899. slv-ddrc-apu-cfg {
  900. cell-id = <0x2dc>;
  901. label = "slv-ddrc-apu-cfg";
  902. qcom,buswidth = <0x04>;
  903. qcom,ap-owned;
  904. qcom,bus-dev = <0x04>;
  905. qcom,slv-rpm-id = <0xc9>;
  906. linux,phandle = <0x15>;
  907. phandle = <0x15>;
  908. };
  909.  
  910. slv-ddrc-mpu0-cfg {
  911. cell-id = <0x2dd>;
  912. label = "slv-ddrc-mpu0-cfg";
  913. qcom,buswidth = <0x04>;
  914. qcom,ap-owned;
  915. qcom,bus-dev = <0x04>;
  916. qcom,slv-rpm-id = <0xca>;
  917. linux,phandle = <0x0b>;
  918. phandle = <0x0b>;
  919. };
  920.  
  921. slv-ddrc-mpu1-cfg {
  922. cell-id = <0x2de>;
  923. label = "slv-ddrc-mpu1-cfg";
  924. qcom,buswidth = <0x04>;
  925. qcom,ap-owned;
  926. qcom,bus-dev = <0x04>;
  927. qcom,slv-rpm-id = <0xcb>;
  928. linux,phandle = <0x0a>;
  929. phandle = <0x0a>;
  930. };
  931.  
  932. slv-ddrc-mpu2-cfg {
  933. cell-id = <0x2de>;
  934. label = "slv-ddrc-mpu2-cfg";
  935. qcom,buswidth = <0x04>;
  936. qcom,ap-owned;
  937. qcom,bus-dev = <0x04>;
  938. qcom,slv-rpm-id = <0xd2>;
  939. linux,phandle = <0x1e>;
  940. phandle = <0x1e>;
  941. };
  942.  
  943. slv-ess-vmidmt-cfg {
  944. cell-id = <0x2df>;
  945. label = "slv-ess-vmidmt-cfg";
  946. qcom,buswidth = <0x04>;
  947. qcom,ap-owned;
  948. qcom,bus-dev = <0x04>;
  949. qcom,slv-rpm-id = <0xd3>;
  950. linux,phandle = <0x1f>;
  951. phandle = <0x1f>;
  952. };
  953.  
  954. slv-ess-apu-cfg {
  955. cell-id = <0x2e0>;
  956. label = "slv-ess-apu-cfg";
  957. qcom,buswidth = <0x04>;
  958. qcom,ap-owned;
  959. qcom,bus-dev = <0x04>;
  960. qcom,slv-rpm-id = <0xd4>;
  961. linux,phandle = <0x0f>;
  962. phandle = <0x0f>;
  963. };
  964.  
  965. slv-usb2-cfg {
  966. cell-id = <0x2e1>;
  967. label = "slv-usb2-cfg";
  968. qcom,buswidth = <0x04>;
  969. qcom,ap-owned;
  970. qcom,bus-dev = <0x04>;
  971. qcom,slv-rpm-id = <0xd5>;
  972. linux,phandle = <0x25>;
  973. phandle = <0x25>;
  974. };
  975.  
  976. slv-blsp-cfg {
  977. cell-id = <0x2e2>;
  978. label = "slv-blsp-cfg";
  979. qcom,buswidth = <0x04>;
  980. qcom,ap-owned;
  981. qcom,bus-dev = <0x04>;
  982. qcom,slv-rpm-id = <0xd6>;
  983. linux,phandle = <0x24>;
  984. phandle = <0x24>;
  985. };
  986.  
  987. slv-qpic-cfg {
  988. cell-id = <0x2e3>;
  989. label = "slv-qpic-cfg";
  990. qcom,buswidth = <0x04>;
  991. qcom,ap-owned;
  992. qcom,bus-dev = <0x04>;
  993. qcom,slv-rpm-id = <0xd7>;
  994. linux,phandle = <0x0c>;
  995. phandle = <0x0c>;
  996. };
  997.  
  998. slv-sdcc-cfg {
  999. cell-id = <0x2e4>;
  1000. label = "slv-sdcc-cfg";
  1001. qcom,buswidth = <0x04>;
  1002. qcom,ap-owned;
  1003. qcom,bus-dev = <0x04>;
  1004. qcom,slv-rpm-id = <0xd8>;
  1005. linux,phandle = <0x29>;
  1006. phandle = <0x29>;
  1007. };
  1008.  
  1009. slv-wss0-vmidmt-cfg {
  1010. cell-id = <0x2e5>;
  1011. label = "slv-wss0-vmidmt-cfg";
  1012. qcom,buswidth = <0x04>;
  1013. qcom,ap-owned;
  1014. qcom,bus-dev = <0x04>;
  1015. qcom,slv-rpm-id = <0xd9>;
  1016. linux,phandle = <0x18>;
  1017. phandle = <0x18>;
  1018. };
  1019.  
  1020. slv-wss0-apu-cfg {
  1021. cell-id = <0x2e6>;
  1022. label = "slv-wss0-apu-cfg";
  1023. qcom,buswidth = <0x04>;
  1024. qcom,ap-owned;
  1025. qcom,bus-dev = <0x04>;
  1026. qcom,slv-rpm-id = <0xda>;
  1027. linux,phandle = <0x14>;
  1028. phandle = <0x14>;
  1029. };
  1030.  
  1031. slv-wss1-vmidmt-cfg {
  1032. cell-id = <0x2e7>;
  1033. label = "slv-wss1-vmidmt-cfg";
  1034. qcom,buswidth = <0x04>;
  1035. qcom,ap-owned;
  1036. qcom,bus-dev = <0x04>;
  1037. qcom,slv-rpm-id = <0xdb>;
  1038. linux,phandle = <0x28>;
  1039. phandle = <0x28>;
  1040. };
  1041.  
  1042. slv-wss1-apu-cfg {
  1043. cell-id = <0x2e8>;
  1044. label = "slv-wss1-apu-cfg";
  1045. qcom,buswidth = <0x04>;
  1046. qcom,ap-owned;
  1047. qcom,bus-dev = <0x04>;
  1048. qcom,slv-rpm-id = <0xdc>;
  1049. linux,phandle = <0x09>;
  1050. phandle = <0x09>;
  1051. };
  1052.  
  1053. slv-pcnoc-snoc {
  1054. cell-id = <0x271b>;
  1055. label = "slv-pcnoc-snoc";
  1056. qcom,buswidth = <0x04>;
  1057. qcom,ap-owned;
  1058. qcom,bus-dev = <0x04>;
  1059. qcom,slv-rpm-id = <0x2d>;
  1060. linux,phandle = <0x2b>;
  1061. phandle = <0x2b>;
  1062. };
  1063.  
  1064. slv-srvc-pcnoc {
  1065. cell-id = <0x2e9>;
  1066. label = "slv-srvc-pcnoc";
  1067. qcom,buswidth = <0x04>;
  1068. qcom,ap-owned;
  1069. qcom,bus-dev = <0x04>;
  1070. qcom,slv-rpm-id = <0xdd>;
  1071. linux,phandle = <0x26>;
  1072. phandle = <0x26>;
  1073. };
  1074.  
  1075. slv-snoc-ddrc-m1 {
  1076. cell-id = <0x2ea>;
  1077. label = "slv-snoc-ddrc-m1";
  1078. qcom,buswidth = <0x08>;
  1079. qcom,ap-owned;
  1080. qcom,bus-dev = <0x31>;
  1081. qcom,slv-rpm-id = <0xde>;
  1082. linux,phandle = <0x32>;
  1083. phandle = <0x32>;
  1084. };
  1085.  
  1086. slv-a7ss {
  1087. cell-id = <0x2eb>;
  1088. label = "slv-a7ss";
  1089. qcom,buswidth = <0x04>;
  1090. qcom,ap-owned;
  1091. qcom,bus-dev = <0x31>;
  1092. qcom,slv-rpm-id = <0xdf>;
  1093. linux,phandle = <0x39>;
  1094. phandle = <0x39>;
  1095. };
  1096.  
  1097. slv-ocimem {
  1098. cell-id = <0x249>;
  1099. label = "slv-ocimem";
  1100. qcom,buswidth = <0x08>;
  1101. qcom,ap-owned;
  1102. qcom,bus-dev = <0x31>;
  1103. qcom,slv-rpm-id = <0x1a>;
  1104. linux,phandle = <0x46>;
  1105. phandle = <0x46>;
  1106. };
  1107.  
  1108. slv-wss0-cfg {
  1109. cell-id = <0x2ec>;
  1110. label = "slv-wss0-cfg";
  1111. qcom,buswidth = <0x04>;
  1112. qcom,ap-owned;
  1113. qcom,bus-dev = <0x31>;
  1114. qcom,slv-rpm-id = <0xe0>;
  1115. linux,phandle = <0x37>;
  1116. phandle = <0x37>;
  1117. };
  1118.  
  1119. slv-wss1-cfg {
  1120. cell-id = <0x2ed>;
  1121. label = "slv-wss1-cfg";
  1122. qcom,buswidth = <0x04>;
  1123. qcom,ap-owned;
  1124. qcom,bus-dev = <0x31>;
  1125. qcom,slv-rpm-id = <0xe1>;
  1126. linux,phandle = <0x36>;
  1127. phandle = <0x36>;
  1128. };
  1129.  
  1130. slv-pcie {
  1131. cell-id = <0x2ee>;
  1132. label = "slv-pcie";
  1133. qcom,buswidth = <0x08>;
  1134. qcom,ap-owned;
  1135. qcom,bus-dev = <0x31>;
  1136. qcom,slv-rpm-id = <0xe2>;
  1137. linux,phandle = <0x30>;
  1138. phandle = <0x30>;
  1139. };
  1140.  
  1141. slv-usb3-cfg {
  1142. cell-id = <0x2ef>;
  1143. label = "slv-usb3-cfg";
  1144. qcom,buswidth = <0x04>;
  1145. qcom,ap-owned;
  1146. qcom,bus-dev = <0x31>;
  1147. qcom,slv-rpm-id = <0xe3>;
  1148. linux,phandle = <0x34>;
  1149. phandle = <0x34>;
  1150. };
  1151.  
  1152. slv-crypto-cfg {
  1153. cell-id = <0x2f0>;
  1154. label = "slv-crypto-cfg";
  1155. qcom,buswidth = <0x04>;
  1156. qcom,ap-owned;
  1157. qcom,bus-dev = <0x31>;
  1158. qcom,slv-rpm-id = <0xe4>;
  1159. linux,phandle = <0x38>;
  1160. phandle = <0x38>;
  1161. };
  1162.  
  1163. slv-ess-cfg {
  1164. cell-id = <0x2f1>;
  1165. label = "slv-ess-cfg";
  1166. qcom,buswidth = <0x04>;
  1167. qcom,ap-owned;
  1168. qcom,bus-dev = <0x31>;
  1169. qcom,slv-rpm-id = <0xe5>;
  1170. linux,phandle = <0x35>;
  1171. phandle = <0x35>;
  1172. };
  1173.  
  1174. slv-qdss-stm {
  1175. cell-id = <0x24c>;
  1176. label = "slv-qdss-stm";
  1177. qcom,buswidth = <0x04>;
  1178. qcom,ap-owned;
  1179. qcom,bus-dev = <0x31>;
  1180. qcom,slv-rpm-id = <0x1e>;
  1181. linux,phandle = <0x3a>;
  1182. phandle = <0x3a>;
  1183. };
  1184.  
  1185. slv-srvc-snoc {
  1186. cell-id = <0x2f2>;
  1187. label = "slv-srvc-snoc";
  1188. qcom,buswidth = <0x08>;
  1189. qcom,ap-owned;
  1190. qcom,bus-dev = <0x31>;
  1191. qcom,slv-rpm-id = <0xe6>;
  1192. linux,phandle = <0x33>;
  1193. phandle = <0x33>;
  1194. };
  1195. };
  1196.  
  1197. interrupt-controller@b000000 {
  1198. compatible = "qcom,msm-qgic2";
  1199. interrupt-controller;
  1200. #interrupt-cells = <0x03>;
  1201. reg = <0xb000000 0x1000 0xb002000 0x1000>;
  1202. linux,phandle = <0x01>;
  1203. phandle = <0x01>;
  1204. };
  1205.  
  1206. counter {
  1207. compatible = "qcom,qca-gcnt";
  1208. reg = <0x4a1000 0x04>;
  1209. };
  1210.  
  1211. clock-controller@1800000 {
  1212. compatible = "qcom,gcc-ipq40xx";
  1213. #clock-cells = <0x01>;
  1214. #reset-cells = <0x01>;
  1215. reg = <0x1800000 0x60000>;
  1216. linux,phandle = <0x02>;
  1217. phandle = <0x02>;
  1218. };
  1219.  
  1220. clock-controller@7700038 {
  1221. compatible = "qcom,adcc-ipq40xx";
  1222. #clock-cells = <0x01>;
  1223. #reset-cells = <0x01>;
  1224. reg = <0x7700038 0x1dc>;
  1225. status = "disabled";
  1226. };
  1227.  
  1228. timer {
  1229. compatible = "arm,armv7-timer";
  1230. interrupts = <0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x04 0xf08 0x01 0x01 0xf08>;
  1231. clock-frequency = <0x2dc6c00>;
  1232. };
  1233.  
  1234. restart@4ab000 {
  1235. compatible = "qcom,pshold";
  1236. reg = <0x4ab000 0x04>;
  1237. };
  1238.  
  1239. watchdog@b017000 {
  1240. compatible = "qcom,kpss-wdt-ipq40xx";
  1241. reg = <0xb017000 0x40>;
  1242. interrupt-names = "bark_irq";
  1243. interrupts = <0x00 0x03 0x00>;
  1244. clocks = <0x47>;
  1245. timeout-sec = <0x0a>;
  1246. wdt_res = <0x04>;
  1247. wdt_en = <0x08>;
  1248. wdt_bark_time = <0x10>;
  1249. wdt_bite_time = <0x14>;
  1250. status = "ok";
  1251. };
  1252.  
  1253. a7ss_base@b088000 {
  1254. compatible = "qcom,arm-cortex-acc";
  1255. reg = <0xb088000 0x1000>;
  1256. };
  1257.  
  1258. pinctrl@0x01000000 {
  1259. compatible = "qcom,ipq40xx-pinctrl";
  1260. reg = <0x1000000 0x300000>;
  1261. gpio-controller;
  1262. #gpio-cells = <0x02>;
  1263. interrupt-controller;
  1264. #interrupt-cells = <0x02>;
  1265. interrupts = <0x00 0xd0 0x00>;
  1266. linux,phandle = <0x4a>;
  1267. phandle = <0x4a>;
  1268.  
  1269. serial_pinmux {
  1270. linux,phandle = <0x48>;
  1271. phandle = <0x48>;
  1272.  
  1273. mux {
  1274. pins = "gpio60\0gpio61";
  1275. function = "blsp_uart0";
  1276. bias-disable;
  1277. };
  1278. };
  1279.  
  1280. spi_0_pinmux {
  1281. linux,phandle = <0x49>;
  1282. phandle = <0x49>;
  1283.  
  1284. mux {
  1285. pins = "gpio54\0gpio55\0gpio56\0gpio57";
  1286. function = "blsp_spi0";
  1287. bias-disable;
  1288. };
  1289. };
  1290.  
  1291. i2c_0_pinmux {
  1292. linux,phandle = <0x4f>;
  1293. phandle = <0x4f>;
  1294.  
  1295. mux {
  1296. pins = "gpio58\0gpio59";
  1297. function = "blsp_i2c0";
  1298. bias-disable;
  1299. };
  1300. };
  1301. };
  1302.  
  1303. serial@78af000 {
  1304. compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
  1305. reg = <0x78af000 0x200>;
  1306. interrupts = <0x00 0x6b 0x00>;
  1307. status = "ok";
  1308. clocks = <0x02 0x1a 0x02 0x15>;
  1309. clock-names = "core\0iface";
  1310. pinctrl-0 = <0x48>;
  1311. pinctrl-names = "default";
  1312. };
  1313.  
  1314. serial@78b0000 {
  1315. compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
  1316. reg = <0x78b0000 0x200>;
  1317. interrupts = <0x00 0x6c 0x00>;
  1318. status = "disabled";
  1319. clocks = <0x02 0x1b 0x02 0x15>;
  1320. clock-names = "core\0iface";
  1321. };
  1322.  
  1323. qcom,sps {
  1324. compatible = "qcom,msm_sps_4k";
  1325. qcom,device-type = <0x03>;
  1326. qcom,pipe-attr-ee;
  1327. };
  1328.  
  1329. spi@78b5000 {
  1330. compatible = "qcom,spi-qup-v2";
  1331. #address-cells = <0x01>;
  1332. #size-cells = <0x00>;
  1333. reg-names = "spi_physical\0spi_bam_physical";
  1334. reg = <0x78b5000 0x600 0x7884000 0x23000>;
  1335. interrupt-names = "spi_irq\0spi_bam_irq";
  1336. interrupts = <0x00 0x5f 0x00 0x00 0xee 0x00>;
  1337. spi-max-frequency = <0x16e3600>;
  1338. clocks = <0x02 0x17 0x02 0x15>;
  1339. clock-names = "core_clk\0iface_clk";
  1340. qcom,infinite-mode = <0x00>;
  1341. qcom,use-bam;
  1342. qcom,bam-consumer-pipe-index = <0x04>;
  1343. qcom,bam-producer-pipe-index = <0x05>;
  1344. qcom,master-id = <0x00>;
  1345. status = "ok";
  1346. pinctrl-0 = <0x49>;
  1347. pinctrl-names = "default";
  1348. qcom,gpio-cs1 = <0x4a 0x3f 0x00>;
  1349.  
  1350. m25p80@0 {
  1351. #address-cells = <0x01>;
  1352. #size-cells = <0x01>;
  1353. compatible = "n25q128a11";
  1354. reg = <0x00>;
  1355. linux,modalias = "m25p80\0n25q128a11";
  1356. spi-max-frequency = <0x16e3600>;
  1357. use-default-sizes;
  1358. };
  1359. };
  1360.  
  1361. qcom,nand@7980000 {
  1362. compatible = "qcom,msm-nand";
  1363. reg = <0x7980000 0x40000 0x7984000 0x1a000>;
  1364. reg-names = "nand_phys\0bam_phys";
  1365. interrupts = <0x00 0x65 0x00>;
  1366. interrupt-names = "bam_irq";
  1367. qcom,msm-bus,name = "qpic_nand";
  1368. qcom,msm-bus,num-cases = <0x02>;
  1369. qcom,msm-bus,num-paths = <0x01>;
  1370. qcom,msm-bus,vectors-KBps = <0x5b 0x200 0x00 0x00 0x5b 0x200 0x61a80 0xc3500>;
  1371. clock-names = "iface_clk\0core_clk";
  1372. clocks = <0x02 0x2b 0x02 0x2c>;
  1373. status = "disabled";
  1374. };
  1375.  
  1376. tcsr@194b000 {
  1377. compatible = "qcom,tcsr";
  1378. reg = <0x194b000 0x100>;
  1379. qcom,usb-hsphy-mode-select = <0xe700e7>;
  1380. status = "ok";
  1381. };
  1382.  
  1383. ess_tcsr@1953000 {
  1384. compatible = "qcom,tcsr";
  1385. reg = <0x1953000 0x1000>;
  1386. qcom,ess-interface-select = <0x00>;
  1387. };
  1388.  
  1389. ssphy@0 {
  1390. compatible = "qca,uni-ssphy";
  1391. reg = <0x9a000 0x800>;
  1392. reg-names = "phy_base";
  1393. resets = <0x02 0x0c>;
  1394. reset-names = "por_rst";
  1395. qca,host = <0x01>;
  1396. qca,emulation = <0x00>;
  1397. status = "ok";
  1398. linux,phandle = <0x4c>;
  1399. phandle = <0x4c>;
  1400. };
  1401.  
  1402. ssphy@1 {
  1403. compatible = "qca,dummy-ssphy";
  1404. status = "ok";
  1405. linux,phandle = <0x4e>;
  1406. phandle = <0x4e>;
  1407. };
  1408.  
  1409. hsphy@a6000 {
  1410. compatible = "qca,baldur-usb3-hsphy";
  1411. reg = <0xa6000 0x40>;
  1412. reg-names = "phy_base";
  1413. resets = <0x02 0x0d 0x02 0x0e>;
  1414. reset-names = "por_rst\0srif_rst";
  1415. qca,host = <0x01>;
  1416. qca,emulation = <0x00>;
  1417. status = "ok";
  1418. linux,phandle = <0x4b>;
  1419. phandle = <0x4b>;
  1420. };
  1421.  
  1422. hsphy@a8000 {
  1423. compatible = "qca,baldur-usb2-hsphy";
  1424. reg = <0xa8000 0x40>;
  1425. reg-names = "phy_base";
  1426. resets = <0x02 0x0f 0x02 0x10>;
  1427. reset-names = "por_rst\0srif_rst";
  1428. qca,host = <0x01>;
  1429. qca,emulation = <0x00>;
  1430. status = "ok";
  1431. linux,phandle = <0x4d>;
  1432. phandle = <0x4d>;
  1433. };
  1434.  
  1435. usb3@8a00000 {
  1436. compatible = "qca,dwc3";
  1437. #address-cells = <0x01>;
  1438. #size-cells = <0x01>;
  1439. ranges;
  1440. reg = <0x8af8800 0x100>;
  1441. reg-names = "qscratch_base";
  1442. clocks = <0x02 0x37 0x02 0x38 0x02 0x39>;
  1443. clock-names = "master\0sleep\0mock_utmi";
  1444. qca,host = <0x01>;
  1445. status = "ok";
  1446.  
  1447. dwc3@8a00000 {
  1448. compatible = "snps,dwc3";
  1449. reg = <0x8a00000 0xf8000>;
  1450. interrupts = <0x00 0x84 0x00>;
  1451. usb-phy = <0x4b 0x4c>;
  1452. phy-names = "usb2-phy\0usb3-phy";
  1453. tx-fifo-resize;
  1454. dr_mode = "host";
  1455. usb2-susphy-quirk;
  1456. usb2-host-discon-quirk;
  1457. usb2-host-discon-phy-misc-reg = <0x24>;
  1458. usb2-host-discon-mask = <0x100>;
  1459. };
  1460. };
  1461.  
  1462. usb2@6000000 {
  1463. compatible = "qca,dwc3";
  1464. #address-cells = <0x01>;
  1465. #size-cells = <0x01>;
  1466. ranges;
  1467. reg = <0x60f8800 0x100>;
  1468. reg-names = "qscratch_base";
  1469. clocks = <0x02 0x34 0x02 0x35 0x02 0x36>;
  1470. clock-names = "master\0sleep\0mock_utmi";
  1471. qca,host = <0x01>;
  1472. status = "ok";
  1473.  
  1474. dwc3@6000000 {
  1475. compatible = "snps,dwc3";
  1476. reg = <0x6000000 0xf8000>;
  1477. interrupts = <0x00 0x88 0x00>;
  1478. usb-phy = <0x4d 0x4e>;
  1479. phy-names = "usb2-phy\0usb3-phy";
  1480. tx-fifo-resize;
  1481. dr_mode = "host";
  1482. usb2-susphy-quirk;
  1483. usb2-host-discon-quirk;
  1484. usb2-host-discon-phy-misc-reg = <0x24>;
  1485. usb2-host-discon-mask = <0x100>;
  1486. };
  1487. };
  1488.  
  1489. rng@0x00022000 {
  1490. compatible = "qcom,prng";
  1491. reg = <0x22000 0x140>;
  1492. clocks = <0x02 0x2a>;
  1493. clock-names = "core";
  1494. };
  1495.  
  1496. i2c@78b7000 {
  1497. compatible = "qcom,i2c-msm-v2";
  1498. #address-cells = <0x01>;
  1499. #size-cells = <0x00>;
  1500. reg-names = "qup_phys_addr\0bam_phys_addr";
  1501. reg = <0x78b7000 0x600 0x7884000 0x23000>;
  1502. interrupt-names = "qup_irq\0bam_irq";
  1503. interrupts = <0x00 0x61 0x00 0x00 0xee 0x00>;
  1504. clocks = <0x02 0x15 0x02 0x16>;
  1505. clock-names = "iface_clk\0core_clk";
  1506. qcom,clk-freq-out = <0x186a0>;
  1507. qcom,clk-freq-in = <0x122ae10>;
  1508. qcom,noise-rjct-scl = <0x00>;
  1509. qcom,noise-rjct-sda = <0x00>;
  1510. qcom,bam-pipe-idx-cons = <0x08>;
  1511. qcom,bam-pipe-idx-prod = <0x09>;
  1512. qcom,master-id = <0x00>;
  1513. status = "ok";
  1514. pinctrl-0 = <0x4f>;
  1515. pinctrl-names = "i2c_active\0i2c_sleep";
  1516.  
  1517. gpio@20 {
  1518. compatible = "nxp,pca9534";
  1519. reg = <0x20>;
  1520. gpio-controller;
  1521. #gpio-cells = <0x02>;
  1522. };
  1523. };
  1524.  
  1525. qcrypto@8e20000 {
  1526. compatible = "qcom,qcrypto";
  1527. reg = <0x8e20000 0x20000 0x8e04000 0x20000>;
  1528. reg-names = "crypto-base\0crypto-bam-base";
  1529. interrupts = <0x00 0xcf 0x00>;
  1530. qcom,bam-pipe-pair = <0x01>;
  1531. qcom,ce-hw-instance = <0x00>;
  1532. qcom,ce-hw-shared = <0x01>;
  1533. qcom,ce-device = <0x00>;
  1534. qcom,ce-opp-freq = <0x7735940>;
  1535. clocks = <0x02 0x22 0x02 0x21 0x02 0x20>;
  1536. clock-names = "core_clk\0bus_clk\0iface_clk";
  1537. status = "ok";
  1538. };
  1539.  
  1540. qcedev@8e20000 {
  1541. compatible = "qcom,qcedev";
  1542. reg = <0x8e20000 0x20000 0x8e04000 0x20000>;
  1543. reg-names = "crypto-base\0crypto-bam-base";
  1544. interrupts = <0x00 0xcf 0x00>;
  1545. qcom,bam-pipe-pair = <0x01>;
  1546. qcom,ce-hw-instance = <0x00>;
  1547. qcom,ce-hw-shared = <0x01>;
  1548. qcom,ce-device = <0x00>;
  1549. qcom,ce-opp-freq = <0x7735940>;
  1550. clocks = <0x02 0x22 0x02 0x21 0x02 0x20>;
  1551. clock-names = "core_clk\0bus_clk\0iface_clk";
  1552. status = "ok";
  1553. };
  1554.  
  1555. tcsr@1949000 {
  1556. compatible = "qcom,tcsr";
  1557. reg = <0x1949000 0x100>;
  1558. qcom,wifi_glb_cfg = <0x41000000>;
  1559. };
  1560.  
  1561. tcsr@1957000 {
  1562. compatible = "qcom,tcsr";
  1563. reg = <0x1957000 0x100>;
  1564. qcom,wifi_noc_memtype_m0_m2 = <0x2222222>;
  1565. };
  1566.  
  1567. wifi@a000000 {
  1568. compatible = "qca,wifi-ipq40xx";
  1569. reg = <0xa000000 0x200000>;
  1570. core-id = <0x00>;
  1571. resets = <0x02 0x00 0x02 0x01 0x02 0x02 0x02 0x03 0x02 0x04 0x02 0x05>;
  1572. reset-names = "wifi_cpu_init\0wifi_radio_srif\0wifi_radio_warm\0wifi_radio_cold\0wifi_core_warm\0wifi_core_cold";
  1573. clocks = <0x02 0x3a 0x02 0x3b 0x02 0x3c>;
  1574. clock-names = "wifi_wcss_cmd\0wifi_wcss_ref\0wifi_wcss_rtc";
  1575. interrupts = <0x00 0x20 0x01 0x00 0x21 0x01 0x00 0x22 0x01 0x00 0x23 0x01 0x00 0x24 0x01 0x00 0x25 0x01 0x00 0x26 0x01 0x00 0x27 0x01 0x00 0x28 0x01 0x00 0x29 0x01 0x00 0x2a 0x01 0x00 0x2b 0x01 0x00 0x2c 0x01 0x00 0x2d 0x01 0x00 0x2e 0x01 0x00 0x2f 0x01 0x00 0xa8 0x00>;
  1576. interrupt-names = "msi0\0msi1\0msi2\0msi3\0msi4\0msi5\0msi6\0msi7\0msi8\0msi9\0msi10\0msi11\0msi12\0msi13\0msi14\0msi15\0legacy";
  1577. status = "ok";
  1578. qca,msi_addr = <0xb006040>;
  1579. qca,msi_base = <0x40>;
  1580. };
  1581.  
  1582. wifi@a800000 {
  1583. compatible = "qca,wifi-ipq40xx";
  1584. reg = <0xa800000 0x200000>;
  1585. core-id = <0x01>;
  1586. resets = <0x02 0x06 0x02 0x07 0x02 0x08 0x02 0x09 0x02 0x0a 0x02 0x0b>;
  1587. reset-names = "wifi_cpu_init\0wifi_radio_srif\0wifi_radio_warm\0wifi_radio_cold\0wifi_core_warm\0wifi_core_cold";
  1588. clocks = <0x02 0x3d 0x02 0x3e 0x02 0x3f>;
  1589. clock-names = "wifi_wcss_cmd\0wifi_wcss_ref\0wifi_wcss_rtc";
  1590. interrupts = <0x00 0x30 0x01 0x00 0x31 0x01 0x00 0x32 0x01 0x00 0x33 0x01 0x00 0x34 0x01 0x00 0x35 0x01 0x00 0x36 0x01 0x00 0x37 0x01 0x00 0x38 0x01 0x00 0x39 0x01 0x00 0x3a 0x01 0x00 0x3b 0x01 0x00 0x3c 0x01 0x00 0x3d 0x01 0x00 0x3e 0x01 0x00 0x3f 0x01 0x00 0xa9 0x00>;
  1591. interrupt-names = "msi0\0msi1\0msi2\0msi3\0msi4\0msi5\0msi6\0msi7\0msi8\0msi9\0msi10\0msi11\0msi12\0msi13\0msi14\0msi15\0legacy";
  1592. status = "ok";
  1593. qca,msi_addr = <0xb006040>;
  1594. qca,msi_base = <0x50>;
  1595. };
  1596.  
  1597. qcom,pcie@80000 {
  1598. compatible = "qcom,msm_pcie";
  1599. cell-index = <0x00>;
  1600. qcom,ctrl-amt = <0x01>;
  1601. reg = <0x80000 0x2000 0x99000 0x800 0x40000000 0xf1d 0x40000f20 0xa8 0x40100000 0x1000 0x40200000 0x100000 0x40300000 0xd00000>;
  1602. reg-names = "parf\0phy\0dm_core\0elbi\0conf\0io\0bars";
  1603. #address-cells = <0x00>;
  1604. interrupt-parent = <0x50>;
  1605. interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c>;
  1606. #interrupt-cells = <0x01>;
  1607. interrupt-map-mask = <0xffffffff>;
  1608. interrupt-map = <0x00 0x01 0x00 0x8d 0x00 0x01 0x01 0x00 0x8e 0x00 0x02 0x01 0x00 0x8f 0x00 0x03 0x01 0x00 0x90 0x00 0x04 0x01 0x00 0x91 0x00 0x05 0x01 0x00 0x92 0x00 0x06 0x01 0x00 0x93 0x00 0x07 0x01 0x00 0x94 0x00 0x08 0x01 0x00 0x95 0x00 0x09 0x01 0x00 0x96 0x00 0x0a 0x01 0x00 0x97 0x00 0x0b 0x01 0x00 0x98 0x00>;
  1609. interrupt-names = "int_msi\0int_a\0int_b\0int_c\0int_d\0int_pls_pme\0int_pme_legacy\0int_pls_err\0int_aer_legacy\0int_pls_link_up\0int_pls_link_down\0int_bridge_flush_n\0int_wake";
  1610. qcom,ep-latency = <0x0a>;
  1611. clocks = <0x02 0x26 0x02 0x27 0x02 0x28>;
  1612. clock-names = "pcie_0_cfg_ahb_clk\0pcie_0_mstr_axi_clk\0pcie_0_slv_axi_clk";
  1613. max-clock-frequency-hz = <0x00 0x00 0x00>;
  1614. resets = <0x02 0x1c 0x02 0x1b 0x02 0x1a 0x02 0x19 0x02 0x18 0x02 0x17 0x02 0x16 0x02 0x15 0x02 0x14 0x02 0x13 0x02 0x12 0x02 0x11>;
  1615. reset-names = "pcie_rst_axi_m_ares\0pcie_rst_axi_s_ares\0pcie_rst_pipe_ares\0pcie_rst_axi_m_vmidmt_ares\0pcie_rst_axi_s_xpu_ares\0pcie_rst_parf_xpu_ares\0pcie_rst_phy_ares\0pcie_rst_axi_m_sticky_ares\0pcie_rst_pipe_sticky_ares\0pcie_rst_pwr_ares\0pcie_rst_ahb_res\0pcie_rst_phy_ahb_ares";
  1616. status = "disabled";
  1617. linux,phandle = <0x50>;
  1618. phandle = <0x50>;
  1619. };
  1620.  
  1621. ledc@1937000 {
  1622. compatible = "qca,ledc";
  1623. reg = <0x1937000 0x20070>;
  1624. reg-names = "ledc_base_addr";
  1625. qcom,tcsr_ledc_values = <0x320193 0x14720800 0x20d 0x00 0x00 0xffffffff 0x00 0x07 0x7d0010 0x00 0x10482090 0x3fffdfc>;
  1626. qcom,ledc_blink_indices_cnt = <0x00>;
  1627. qcom,ledc_blink_indices = <0x00>;
  1628. status = "disabled";
  1629. };
  1630.  
  1631. pmu {
  1632. compatible = "arm,cortex-a7-pmu";
  1633. interrupts = <0x01 0x07 0xf04>;
  1634. };
  1635.  
  1636. sdhci@7824000 {
  1637. compatible = "qcom,sdhci-msm-v4";
  1638. reg = <0x7824900 0x11c 0x7824000 0x800>;
  1639. interrupts = <0x00 0x7b 0x00 0x00 0x8a 0x00>;
  1640. bus-width = <0x08>;
  1641. clocks = <0x02 0x2e 0x02 0x2d>;
  1642. clock-names = "core\0iface";
  1643. status = "disabled";
  1644. };
  1645.  
  1646. ess-switch@c000000 {
  1647. compatible = "qcom,ess-switch";
  1648. reg = <0xc000000 0x80000>;
  1649. switch_access_mode = "local bus";
  1650. resets = <0x02 0x1d 0x02 0x4e 0x02 0x4f 0x02 0x50 0x02 0x51 0x02 0x52>;
  1651. reset-names = "ess_rst\0ess_mac1_clk_dis\0ess_mac2_clk_dis\0ess_mac3_clk_dis\0ess_mac4_clk_dis\0ess_mac5_clk_dis";
  1652. clocks = <0x02 0x23>;
  1653. clock-names = "ess_clk";
  1654. switch_cpu_bmp = <0x01>;
  1655. switch_lan_bmp = <0x1e>;
  1656. switch_wan_bmp = <0x20>;
  1657. switch_mac_mode = <0x00>;
  1658. switch_initvlas = <0x7c 0x54>;
  1659. };
  1660.  
  1661. ess-psgmii@98000 {
  1662. compatible = "qcom,ess-psgmii";
  1663. reg = <0x98000 0x800>;
  1664. psgmii_access_mode = "local bus";
  1665. resets = <0x02 0x4d>;
  1666. reset-names = "psgmii_rst";
  1667. };
  1668.  
  1669. mdio@90000 {
  1670. #address-cells = <0x01>;
  1671. #size-cells = <0x01>;
  1672. compatible = "qcom,ipq40xx-mdio";
  1673. reg = <0x90000 0x64>;
  1674.  
  1675. ethernet-phy@0 {
  1676. reg = <0x00>;
  1677. };
  1678.  
  1679. ethernet-phy@1 {
  1680. reg = <0x01>;
  1681. };
  1682.  
  1683. ethernet-phy@2 {
  1684. reg = <0x02>;
  1685. };
  1686.  
  1687. ethernet-phy@3 {
  1688. reg = <0x03>;
  1689. };
  1690.  
  1691. ethernet-phy@4 {
  1692. reg = <0x04>;
  1693. };
  1694. };
  1695.  
  1696. qca,scm_restart_reason {
  1697. compatible = "qca,scm_restart_reason";
  1698. };
  1699.  
  1700. cpu_freq_ipq40xx {
  1701. compatible = "qca,ipq40xx_freq";
  1702. clock-latency = <0x186a0>;
  1703. qcom,cpufreq-table = <0xbb80 0x30d40 0x7a120 0xad570>;
  1704. };
  1705.  
  1706. edma@c080000 {
  1707. compatible = "qcom,ess-edma";
  1708. reg = <0xc080000 0x8000>;
  1709. qcom,page-mode = <0x00>;
  1710. qcom,rx_head_buf_size = <0x604>;
  1711. qcom,wan_port_id_mask = <0x08>;
  1712. qcom,mdio_supported;
  1713. qcom,phy_mdio_addr_wan = <0x03>;
  1714. qcom,phy_mdio_addr_lan = <0x04>;
  1715. qcom,poll_required = <0x01>;
  1716. qcom,forced_speed = <0x3e8>;
  1717. qcom,forced_duplex = <0x01>;
  1718. interrupts = <0x00 0x41 0x01 0x00 0x42 0x01 0x00 0x43 0x01 0x00 0x44 0x01 0x00 0x45 0x01 0x00 0x46 0x01 0x00 0x47 0x01 0x00 0x48 0x01 0x00 0x49 0x01 0x00 0x4a 0x01 0x00 0x4b 0x01 0x00 0x4c 0x01 0x00 0x4d 0x01 0x00 0x4e 0x01 0x00 0x4f 0x01 0x00 0x50 0x01 0x00 0xf0 0x01 0x00 0xf1 0x01 0x00 0xf2 0x01 0x00 0xf3 0x01 0x00 0xf4 0x01 0x00 0xf5 0x01 0x00 0xf6 0x01 0x00 0xf7 0x01 0x00 0xf8 0x01 0x00 0xf9 0x01 0x00 0xfa 0x01 0x00 0xfb 0x01 0x00 0xfc 0x01 0x00 0xfd 0x01 0x00 0xfe 0x01 0x00 0xff 0x01>;
  1719.  
  1720. gmac0 {
  1721. local-mac-address = [00 00 00 00 00 00];
  1722. };
  1723.  
  1724. gmac1 {
  1725. local-mac-address = [00 00 00 00 00 00];
  1726. };
  1727. };
  1728.  
  1729. reset_button {
  1730. qcom,reset_button_gpio = <0x04>;
  1731. };
  1732. };
  1733.  
  1734. reserved-memory {
  1735. #address-cells = <0x01>;
  1736. #size-cells = <0x01>;
  1737. ranges;
  1738.  
  1739. rsvd1@87000000 {
  1740. reg = <0x87000000 0x500000>;
  1741. no-map;
  1742. };
  1743.  
  1744. wifi_dump@87500000 {
  1745. reg = <0x87500000 0x600000>;
  1746. no-map;
  1747. };
  1748.  
  1749. rsvd2@87B00000 {
  1750. reg = <0x87b00000 0x500000>;
  1751. no-map;
  1752. };
  1753. };
  1754. };
  1755.  
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