module FSM_lab7_part1a(
	 input w,clk,aclr,
    output reg z,
    output reg [8:0] y);
    reg [8:0] state, next;

    localparam [8:0]    A = 9'b000000000,   // kody stanów
            B = 9'b000000011,
            C = 9'b000000101,
            D = 9'b000001001,
            E = 9'b000010001,
            F = 9'b000100001,
            G = 9'b001000001,
            H = 9'b010000001,
            I = 9'b100000001;


  always @(*)		// defenicia przejść
	case (state)

		A: 	if (!w) next = B; 	else next = F;
		B: 	if (!w) next = C; 	else next = F;
		C: 	if (!w) next = D; 	else next = F;
		D: 	if (!w) next = E; 	else next = F;
		E: 	if (!w) next = E; 	else next = F;
		F: 	if (!w) next = B; 	else next = G;
		G: 	if (!w) next = B; 	else next = H;
		H: 	if (!w) next = B; 	else next = I;
		I: 	if (!w) next = B; 	else next = I;

		/*default: 	next = 9'bxxxxxxxxx;*/
	endcase

	always @(posedge clk,negedge aclr)	// defenicja pamęci
		if (~aclr)
			state <= 0;

		else
			state <= next;

	always @(*)			// defenicja wyjść
		z = (state == E) | (state == I);

		always @(*)
// opis funkcji wyjściowych

			case (state)

				A: y= 9'b000000000;
            B: y= 9'b000000011;
            C: y= 9'b000000101;
            D: y= 9'b000001001;
            E: y= 9'b000010001;
            F: y= 9'b000100001;
            G: y= 9'b001000001;
            H: y= 9'b010000001;
            I: y= 9'b100000001;
			endcase

endmodule



module zadanie1v1(
	input [1:0] SW,
	input [1:0] KEY,
	output [9:0] LEDR);

	FSM_lab7_part1a ex(SW[1],KEY[0],SW[0],LEDR[9],LEDR[8:0]);

endmodule