ALU

module my_ald(input logic [1:0] sel, input logic a, input logic b, output logic y);

always_comb
begin
    case(sel)
    2'b00: y = a&b;
    2'b01: y = ~(a&b);
    2'b10: y = a&b;
    2'b11: y = ~(a|b);
    endcase
end
endmodule