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Aug 16th, 2018
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  1. &csi1 {
  2. status = "okay";
  3. pinctrl-names = "default";
  4. pinctrl-0 = <&csi1_pins>;
  5. port {
  6. /* Parallel bus endpoint */
  7. csi1_ep: endpoint {
  8. remote-endpoint = <&ov7670_0>;
  9. bus-width = <8>;
  10. If hsync-active/vsync-active are missing,
  11. embedded BT.656 sync is used */
  12. hsync-active = <0>; /* Active low */
  13. vsync-active = <0>; /* Active low */
  14. data-active = <1>; /* Active high */
  15. pclk-sample = <1>; /* Rising */
  16.  
  17.  
  18. };
  19. };
  20. };
  21.  
  22. &i2c1 {
  23. pinctrl-0 = <&i2c1_pins>;
  24. pinctrl-names = "default";
  25. status = "okay";
  26.  
  27.  
  28. ov7670: camera@21 {
  29. compatible = "ovti,ov7670";
  30. reg = <0x21>;
  31. pinctrl-names = "default";
  32. pinctrl-0 = <&csi1_mclk>;
  33. clocks = <&ccu CLK_CSI1_MCLK>;
  34. clock-names = "xclk";
  35. assigned-clock-rates = <24000000>;
  36.  
  37. port {
  38. ov7670_0: endpoint {
  39. remote-endpoint = <&csi1_ep>;
  40. /* If hsync-active/vsync-active are missing,
  41. embedded BT.656 sync is used */
  42. hsync-active = <0>; /* Active low */
  43. vsync-active = <0>; /* Active low */
  44. data-active = <1>; /* Active high */
  45. pclk-sample = <1>; /* Rising */
  46.  
  47.  
  48.  
  49. };
  50. };
  51. };
  52. };
  53. &pio {
  54. csi1_pins: csi1-pins@0 {
  55. pins =
  56. "PE0","PE2","PE3","PE4","PE5","PE6","PE7","PE8","PE9","PE10","PE11";
  57. function = "csi";
  58. };
  59.  
  60. csi1_mclk: csi1-mclk@0 {
  61. pins = "PE1";
  62. function = "csi";
  63. };
  64.  
  65. i2c1_pins: i2c1 {
  66. pins = "PE21", "PE22";
  67. function = "i2c1";
  68. };
  69. };
  70.  
  71. csi1: csi@1cb4000 {
  72. compatible = "allwinner,sun8i-v3s-csi";
  73. reg = <0x01cb4000 0x1000>;
  74. interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  75. clocks = <&ccu CLK_BUS_CSI>,
  76. <&ccu CLK_CSI1_SCLK>,
  77. <&ccu CLK_DRAM_CSI>;
  78. clock-names = "bus", "mod", "ram";
  79. resets = <&ccu RST_BUS_CSI>;
  80. status = "disabled";
  81. };
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