reg [3:0] ssl_cnt;  // clock divider counter

always @ (posedge sck)
  begin
    if (count==4'b1110)  // divide by 14
       count <= 4'b0000;  // reset to 0
    else count <= count+1;  // increment counter
    ssl  <=  (count == 4'b0000);  // counter decoded, single cycle pulse is generated
  end