library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity new_game is
port ( turn : in std_logic;
		 legal_play : in std_logic;
		 stack_num : in std_logic_vector( 5 downto 0 );
		 address: out std_logic_vector( 5 downto 0 );
		 get_card : out std_logic_vector(5 downto 0);
		 next_turn : out std_logic);
TYPE state_signal IS (S0, S1, S2, DONE);
SIGNAL state : state_signal;

begin
signal add : std_logic_vector (5 downto 0);
add = "000000";
state_update : process (Clock, reset)
	begin
	if Clock = '1' and Clock'EVENT then
		case state is
		when S0 =>
			if turn = '1' then
				state <= S1; else state <= S0;
			end if;
		when S1 =>
			if legal_play = '1' then
			state <= DONE;
			elsif stack_num > add then
				add <= add + "000001";
				state <= S1;
			else state <= S2; end if;
		when S2 =>
			state <= DONE;
		when DONE =>
			state <= S0;
		end case;
	end if;
	end process;

output_logic : process(state)
	begin
	case state is
		when S0 =>
			address = "000000";
			get_card = "000000";
			next_turn = '0';
		when S1 =>
			address = add;
		when S2 =>
			players_mode <= "11";
			play_deck_mode <= "10";
			player_Enable <= '1';
			AI_Enable <= '0';
			request_deal <= '1';
			turn <= '0';
		WHEN DONE =>
			players_mode <= "00";
			play_deck_mode <= "00";
			player_Enable <= '0';
			AI_Enable <= '0';
			request_deal <= '0';
	end case;
	end process;
end behav;