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7isenko

conf

May 23rd, 2022
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  1. `timescale 1ns / 1ps
  2.  
  3. module hypo_nexys(
  4.     input wire CLK100MHZ,
  5.     input wire BTNR,
  6.     input wire [15:0] SW,
  7.     input wire BTNC,
  8.     output wire [15:0] LED
  9. );
  10.  
  11. hypotenuse func(
  12.     .clk_i(CLK100MHZ),
  13.     .rst_i(BTNR),
  14.     .start_i(BTNC),
  15.     .a_bi(SW[7:0]),
  16.     .b_bi(SW[15:8]),
  17.     .c_bo(LED[8:0]),
  18.     .busy_o(LED[15])
  19. );
  20.  
  21. assign LED[14:9] = 0;
  22.  
  23. endmodule
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