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- `timescale 1ns / 1ps
- module hypo_nexys(
- input wire CLK100MHZ,
- input wire BTNR,
- input wire [15:0] SW,
- input wire BTNC,
- output wire [15:0] LED
- );
- hypotenuse func(
- .clk_i(CLK100MHZ),
- .rst_i(BTNR),
- .start_i(BTNC),
- .a_bi(SW[7:0]),
- .b_bi(SW[15:8]),
- .c_bo(LED[8:0]),
- .busy_o(LED[15])
- );
- assign LED[14:9] = 0;
- endmodule
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