module deser7_24(input wire [in-1:0] dataIn,
					input wire clkIn,
					input wire clkToOut,
					output reg [out-1:0] dataOut,
					output reg clkOut
    );
parameter in = 7;
	parameter out = 24;

	reg [in*out-1:0] data = 0;
	integer counterIn = 0;
	integer counterOut = 0;
	integer start = 0;

	always @(posedge clkIn) begin
		counterIn = counterIn + 1;
		if (counterIn > out) begin counterIn = 1; end
		if (counterIn > 1) begin start = 1; end
		case (counterIn)
			1: data[6:0] = dataIn;
			2: data[13:7] = dataIn;
			3:	data[20:14] = dataIn;
			4:	data[27:21] = dataIn;
			5:	data[34:28] = dataIn;
			6:	data[41:35] = dataIn;
			7:	data[48:42] = dataIn;
			8:	data[55:49] = dataIn;
			9:	data[62:56] = dataIn;
			10: data[69:63] = dataIn;
			11: data[76:70] = dataIn;
			12: data[83:77] = dataIn;
			13: data[90:84] = dataIn;
			14: data[97:91] = dataIn;
			15: data[104:98] = dataIn;
			16: data[111:105] = dataIn;
			17: data[118:112] = dataIn;
			18: data[125:119] = dataIn;
			19: data[132:126] = dataIn;
			20: data[139:133] = dataIn;
			21: data[146:140] = dataIn;
			22: data[153:147] = dataIn;
			23: data[160:154] = dataIn;
			24: data[167:161] = dataIn;
			default: ;
		endcase;
	end

	always @(posedge clkToOut or negedge clkToOut) begin
		if (start == 1)
			clkOut = clkToOut;
		else
			clkOut = 0;
	end

	always @(posedge clkToOut) begin
		if (start == 1) begin
			counterOut = counterOut + 1;
			if (counterOut > in) begin counterOut = 1; end
			case (counterOut)
				1:	dataOut = data[23:0];
				2: dataOut = data[47:24];
				3: dataOut = data[71:48];
				4: dataOut = data[95:72];
				5: dataOut = data[119:96];
				6: dataOut = data[143:120];
				7: dataOut = data[167:144];
				default: ;
			endcase;
		end
	end

endmodule