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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. entity halfadder is
  5.   port(a,   b:     in  bit;
  6.        s, c: out bit);
  7. end halfadder;
  9. architecture DATAFLOW of halfadder is
  10. begin
  11.     s   <= A xor B;
  12.     c <= A and B;
  13. end DATAFLOW;
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