AdrianMadajewski

Untitled

Dec 6th, 2020
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  1. LIBRARY ieee;
  2. USE ieee.std_logic_1164.all;
  3.  
  4. ENTITY reklama IS
  5.  
  6.     PORT
  7.     (
  8.     iSW: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
  9.     oHEX0_D, oHEX1_D, oHEX2_D, oHEX3_D, oHEX4_D, oHEX5_D, oHEX6_D, oHEX7_D : OUT STD_LOGIC_VECTOR(0 TO 6)
  10.     );
  11. END reklama;
  12.  
  13. ARCHITECTURE arch OF reklama IS
  14.  
  15. constant SPACJA : std_logic_vector (2 downto 0) := "000";
  16.  
  17. signal M0, M1, M2, M3, M4, M5, M6, M7: STD_LOGIC_VECTOR(2 DOWNTO 0);
  18.  
  19. -- komponenty
  20.  
  21. COMPONENT transkoder --deklaracja transkodera
  22.  
  23.     PORT
  24.     (
  25.         C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
  26.        display : OUT STD_LOGIC_VECTOR(0 TO 6)
  27.      );
  28. END component;
  29.  
  30. COMPONENT multiplekser -- deklaracja mulipteksera
  31.  
  32.     PORT
  33.     (
  34.         S, U0, U1, U2, U3, U4, U5,U6,U7: IN STD_LOGIC_VECTOR(2 DOWNTO 0); --WEKTOR STERUJĄCY I 8 wektorów INFORMACYJNYCH
  35.        M : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
  36.     );
  37.  
  38. END component;
  39.  
  40. BEGIN
  41.  
  42.     MUX7: multiplekser PORT MAP (
  43.         iSW(17 DOWNTO 15),
  44.         iSW(14 DOWNTO 12),
  45.         iSW(11 DOWNTO 9),
  46.         iSW(8 DOWNTO 6),
  47.         iSW(5 DOWNTO 3),
  48.         iSW(2 DOWNTO 0),
  49.         SPACJA,
  50.         SPACJA,
  51.         SPACJA,
  52.         M7
  53.     );
  54.    
  55.     MUX6: multiplekser PORT MAP (
  56.         iSW(17 DOWNTO 15),  
  57.         iSW(11 DOWNTO 9),
  58.         iSW(8 DOWNTO 6),
  59.         iSW(5 DOWNTO 3),
  60.         iSW(2 DOWNTO 0),
  61.         SPACJA,
  62.         SPACJA,
  63.         SPACJA,
  64.         iSW(14 DOWNTO 12),
  65.         M6
  66.     );
  67.    
  68.     MUX5: multiplekser PORT MAP (
  69.         iSW(17 DOWNTO 15),  
  70.         iSW(8 DOWNTO 6),
  71.         iSW(5 DOWNTO 3),
  72.         iSW(2 DOWNTO 0),
  73.         SPACJA,
  74.         SPACJA,
  75.         SPACJA,
  76.         iSW(14 DOWNTO 12),
  77.         iSW(11 DOWNTO 9),
  78.         M5
  79.     );
  80.    
  81.     MUX4: multiplekser PORT MAP (
  82.         iSW(17 DOWNTO 15),  
  83.         iSW(5 DOWNTO 3),
  84.         iSW(2 DOWNTO 0),
  85.         SPACJA,
  86.         SPACJA,
  87.         SPACJA,
  88.         iSW(14 DOWNTO 12),
  89.         iSW(11 DOWNTO 9),
  90.         iSW(8 DOWNTO 6),
  91.         M4
  92.     );
  93.    
  94.     MUX3: multiplekser PORT MAP (
  95.         iSW(17 DOWNTO 15),  
  96.         iSW(2 DOWNTO 0),
  97.         SPACJA,
  98.         SPACJA,
  99.         SPACJA,
  100.         iSW(14 DOWNTO 12),
  101.         iSW(11 DOWNTO 9),
  102.         iSW(8 DOWNTO 6),
  103.         iSW(5 DOWNTO 3),
  104.         M3
  105.     );
  106.    
  107.     MUX2: multiplekser PORT MAP (
  108.         iSW(17 DOWNTO 15),  
  109.         SPACJA,
  110.         SPACJA,
  111.         SPACJA,
  112.         iSW(14 DOWNTO 12),
  113.         iSW(11 DOWNTO 9),
  114.         iSW(8 DOWNTO 6),
  115.         iSW(5 DOWNTO 3),
  116.         iSW(2 DOWNTO 0),
  117.         M2
  118.     );
  119.    
  120.     MUX1: multiplekser PORT MAP (
  121.         iSW(17 DOWNTO 15),  
  122.         SPACJA,
  123.         SPACJA,
  124.         iSW(14 DOWNTO 12),
  125.         iSW(11 DOWNTO 9),
  126.         iSW(8 DOWNTO 6),
  127.         iSW(5 DOWNTO 3),
  128.         iSW(2 DOWNTO 0),
  129.         SPACJA,
  130.         M1
  131.     );
  132.    
  133.     MUX0: multiplekser PORT MAP (
  134.         iSW(17 DOWNTO 15),  
  135.         SPACJA,
  136.         iSW(14 DOWNTO 12),
  137.         iSW(11 DOWNTO 9),
  138.         iSW(8 DOWNTO 6),
  139.         iSW(5 DOWNTO 3),
  140.         iSW(2 DOWNTO 0),
  141.         SPACJA,
  142.         SPACJA,
  143.         M0
  144.     );
  145. -- KONKRETYZACJE KOLEJNYCH MULTIPLEKSERÓW UKŁADU
  146.  
  147.     H07: transkoder PORT MAP (M7, oHEX7_D);
  148.  
  149.     H06: transkoder PORT MAP (M6, oHEX6_D);
  150.    
  151.     H05: transkoder PORT MAP (M5, oHEX5_D);
  152.    
  153.     H04: transkoder PORT MAP (M4, oHEX4_D);
  154.    
  155.     H03: transkoder PORT MAP (M3, oHEX3_D);
  156.    
  157.     H02: transkoder PORT MAP (M2, oHEX2_D);
  158.    
  159.     H01: transkoder PORT MAP (M1, oHEX1_D);
  160.    
  161.     H00: transkoder PORT MAP (M0, oHEX0_D);
  162. -- KONKRETYZACJE KOLEJNYCH TRANSKODERÓW
  163.  
  164. END arch;
  165.  
  166. -- implementacja multipleksera 8 do 1 (wektor 3 bitowy)
  167. LIBRARY ieee;
  168. USE ieee.std_logic_1164.all;
  169.  
  170. ENTITY multiplekser IS
  171.     PORT
  172.     (
  173.         S, U0, U1, U2, U3, U4, U5,U6,U7: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
  174.         M : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
  175.     );
  176.  
  177. END multiplekser;
  178.  
  179. ARCHITECTURE arc OF multiplekser IS
  180.  
  181. BEGIN
  182.  
  183.     M(2) <= (U7(2) and (S(2)) and (not S(1)) and (not S(0))) or
  184.                 (U6(2) and (S(2)) and (not S(1)) and (S(0))) or
  185.                 (U5(2) and (S(2)) and (S(1)) and (S(0))) or
  186.                 (U4(2) and (S(2)) and (S(1)) and (not S(0))) or
  187.                 (U3(2) and (not S(2)) and (S(1)) and (not S(0))) or
  188.                 (U2(2) and (not S(2)) and (S(1)) and (S(0))) or
  189.                 (U1(2) and (not S(2)) and (not S(1)) and (S(0))) or
  190.                 (U0(2) and (not S(2)) and (not S(1)) and (not S(0)));
  191.                
  192.     M(1) <= (U7(1) and (S(2)) and (not S(1)) and (not S(0))) or
  193.                 (U6(1) and (S(2)) and (not S(1)) and (S(0))) or
  194.                 (U5(1) and (S(2)) and (S(1)) and (S(0))) or
  195.                 (U4(1) and (S(2)) and (S(1)) and (not S(0))) or
  196.                 (U3(1) and (not S(2)) and (S(1)) and (not S(0))) or
  197.                 (U2(1) and (not S(2)) and (S(1)) and (S(0))) or
  198.                 (U1(1) and (not S(2)) and (not S(1)) and (S(0))) or
  199.                 (U0(1) and (not S(2)) and (not S(1)) and (not S(0)));
  200.                
  201.     M(0) <= (U7(0) and (S(2)) and (not S(1)) and (not S(0))) or
  202.                 (U6(0) and (S(2)) and (not S(1)) and (S(0))) or
  203.                 (U5(0) and (S(2)) and (S(1)) and (S(0))) or
  204.                 (U4(0) and (S(2)) and (S(1)) and (not S(0))) or
  205.                 (U3(0) and (not S(2)) and (S(1)) and (not S(0))) or
  206.                 (U2(0) and (not S(2)) and (S(1)) and (S(0))) or
  207.                 (U1(0) and (not S(2)) and (not S(1)) and (S(0))) or
  208.                 (U0(0) and (not S(2)) and (not S(1)) and (not S(0)));
  209.  
  210. END arc;
  211.  
  212. -- IMPLEMENTACJA TRANSKODERA
  213. LIBRARY ieee;
  214. USE ieee.std_logic_1164.all;
  215.  
  216. ENTITY transkoder IS
  217.  
  218.     PORT
  219.     (
  220.         C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
  221.         display : OUT STD_LOGIC_VECTOR(0 TO 6) -- S,A,B,C,E
  222.     );
  223. END transkoder;
  224.  
  225. ARCHITECTURE ar OF transkoder IS
  226.  
  227. BEGIN
  228.  
  229.     display(6) <= (not(C(1)) and not(C(0))) or (C(2) and C(1));
  230.     display(5) <= (not(C(2)) and not(C(1)) and not(C(0))) or (C(2) and C(1));
  231.     display(4) <= (not(C(2)) and not(C(1))) or (C(2) and C(1));
  232.     display(3) <= (not(C(2)) and not(C(0))) or (C(2) and C(1));
  233.     display(2) <= (not(C(1)) and not(C(0))) or C(2);
  234.     display(1) <= not(C(1)) or C(2);
  235.     display(0) <= (not(C(2)) and not(C(1)) and not(C(0))) or (C(2) and C(1));
  236.  
  237.    
  238.  
  239. end ar;
  240.  
  241.  
  242.  
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