sid

library ieee;
use ieee.std_logic_1164.all;

entity barramento_teclado is
    port
    (
        clk     : in    std_logic;
        coluna  : in    std_logic_vector(3 downto 0);
        linha       : out   std_logic_vector(3 downto 0);
        tecla       : out   std_logic_vector(3 downto 0)
    );
end entity;

architecture logic of barramento_teclado is
    type state_type is (s0, s1, s2, s3);
    signal state : state_type;
begin
    process (clk)
    begin
        if (rising_edge(clk)) then
            case state is
                when s0=>
                    linha <= "1000";
                    if (coluna = "1000") then
                        tecla <= "0000";
                    elsif (coluna = "0100") then
                        tecla <= "0001";
                    elsif (coluna = "0010") then
                        tecla <= "0010";
                    elsif (coluna = "0001") then
                        tecla <= "0011";
                    else
                                tecla <= "ZZZZ";
                        state <= s1;
                    end if;
                when s1=>
                    linha <= "0100";
                    if (coluna = "1000") then
                        tecla <= "0100";
                    elsif (coluna = "0100") then
                        tecla <= "0101";
                    elsif (coluna = "0010") then
                        tecla <= "0110";
                    elsif (coluna = "0001") then
                        tecla <= "0111";
                    else
                                tecla <= "ZZZZ";
                        state <= s2;
                    end if;
                when s2=>
                    linha <= "0010";
                    if (coluna = "1000") then
                        tecla <= "1000";
                    elsif (coluna = "0100") then
                        tecla <= "1001";
                    elsif (coluna = "0010") then
                        tecla <= "1010";
                    elsif (coluna = "0001") then
                        tecla <= "1011";
                    else
                                tecla <= "ZZZZ";
                        state <= s3;
                    end if;
                when s3=>
                    linha <= "0001";
                    if (coluna = "1000") then
                        tecla <= "1100";
                    elsif (coluna = "0100") then
                        tecla <= "1101";
                    elsif (coluna = "0010") then
                        tecla <= "1110";
                    elsif (coluna = "0001") then
                        tecla <= "1111";
                    else
                                tecla <= "ZZZZ";
                        state <= s0;
                    end if;
            end case;
        end if;
    end process;
end architecture;